HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 271

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.3.5
MAHR is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
11.3.6
MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Bit
31 to 0 MA47 to MA16 All 0
Bit
31 to 16 
15 to 0
Bit Name
Bit Name
MA15 to MA0 All 0
MAC Address High Register (MAHR)
MAC Address Low Register (MALR)
Initial
Value
Initial
Value
All 0
R/W
R/W
R/W
R
R/W
Description
MAC Address Bits
These bits are used to set the upper 32 bits of the MAC
address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), the value set in this register is
H'01234567.
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
MAC Address Bits 15 to 0
These bits are used to set the lower 16 bits of the
MAC address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), the value set in this register is
H'000089AB.
Rev. 6.00 Jun. 12, 2007 Page 239 of 610
Section 11 Ethernet Controller (EtherC)
REJ09B0131-0600