HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 430

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface (HIF)
15.4.2
HIFGSR is a 32-bit register, which can be freely used for handshaking between an external device
connected to the HIF and the software of this LSI. HIFGSR can be read from and written to by the
on-chip CPU. Reading from HIFGSR by an external device should be performed with the HIFRS
pin high, or HIFGSR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Writing
to HIFGSR by an external device should be performed with HIFGSR specified by bits REG5 to
REG0 in HIFIDX and the HIFRS pin low.
15.4.3
HIFSCR is a 32-bit register used to control the HIFRAM access mode and endian setting.
HIFSCR can be read from and written to by the on-chip CPU. Access to HIFSCR by an external
device should be performed with HIFSCR specified by bits REG5 to REG0 in HIFIDX and the
HIFRS pin low.
Rev. 6.00 Jun. 12, 2007 Page 398 of 610
REJ09B0131-0600
Bit
31 to 16
15 to 0
Bit
31 to 12
HIF General Status Register (HIFGSR)
HIF Status/Control Register (HIFSCR)
Bit Name
—
STATUS15 to
STATUS0
Bit Name
—
Initial
Value
All 0
Initial
Value
All 0
All 0
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
General Status
This register can be read from and written to by an
external device connected to the HIF, and by the
on-chip CPU. These bits are initialized only at a
power-on reset.