HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 41

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Classifi-
cation
System
control
Interrupt
Address
bus
Data bus
Bus
control
Abbr.
RES
NMI
IRQ7 to
IRQ0
A25 to A0
D15 to D0
CS0, CS3,
CS4, CS5B,
CS6B
RD
RD/WR
BS
WE1
WE0
WAIT
RAS
CAS
CKE
DQMLU
DQMLL
CE1A
I/O
Input
Input
Input
Output Address Bus
Input/
output
Output Chip Select 0,
Output Read
Output Read/Write
Output Bus Cycle
Output Upper Side
Output Lower Side
Input
Output RAS
Output CAS
Output Clock Enable
Output Upper Side
Output Lower Side
Output PCMCIA Card
Pin Name
Power-On
Reset
Non-Maskable
Interrupt
Interrupt
Request 7 to 0
Data Bus
3, 4, 5B, 6B
Start
Write
Write
Wait
Select
Select
Select Lower
Side
Description
This LSI enters the reset state when this signal goes low.
Non-maskable interrupt request signal. When this pin is not
in use, this signal must be fixed high.
Maskable interrupt request pins.
Level-input or edge-input detection can be selected. When
the edge-input detection is selected, the rising or falling edge
can also be selected.
Outputs addresses.
16-bit bidirectional bus
Chip select signals for external memory and devices.
Indicates that data is read from an external device.
Read/write signal
Indicates start of a bus cycle.
Indicates that bits 15 to 8 of data of external memory or
devices are written to.
Indicates that bits 7 to 0 of data of external memory or
devices are written to.
Input pin used to insert wait cycles when accessing the
external space
Connects to the RAS pin of SDRAM.
Connects to the CAS pin of SDRAM.
Connects to the CKE pin of SDRAM.
Selects bits 15 to 8 of SDRAM data bus.
Selects bits 7 to 0 of SDRAM data bus.
Chip enable for PCMCIA allocated to area 5
Rev. 6.00 Jun. 12, 2007 Page 9 of 610
Section 1 Overview
REJ09B0131-0600