HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 299

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
21
20
19
Bit Name
TC
TDE
TFUF
Initial
value
0
0
0
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R/W
R/W
R/W
R/W
Frame Transmit Complete
Indicates that all the data specified by the transmit
descriptor has been transmitted to the EtherC. The
transfer status is written back to the relevant
descriptor. When 1-frame transmission is completed
for 1-frame/1-buffer processing, or when the last data
in the frame is transmitted and the transmission
descriptor valid bit (TACT) in the next descriptor is not
set for multiple-frame buffer processing, transmission
is completed and this bit is set to 1. After frame
transmission, the E-DMAC writes the transmission
status back to the descriptor.
0: Transfer not complete, or no transfer directive
1: Transfer complete
Transmit Descriptor Empty
Indicates that the transmission descriptor valid bit
(TACT) in the descriptor is not set when the E-DMAC
reads the transmission descriptor when the previous
descriptor is not the last one of the frame for multiple-
buffer frame processing. As a result, an incomplete
frame may be transmitted.
0: Transmit descriptor active bit TACT = 1 detected
1: Transmit descriptor active bit TACT = 0 detected
When transmission descriptor empty (TDE = 1)
occurs, execute a software reset and initiate
transmission. In this case, the address that is stored
in the transmit descriptor list address register
(TDLAR) is transmitted first.
Transmit FIFO Underflow
Indicates that underflow has occurred in the transmit
FIFO during frame transmission. Incomplete data is
sent onto the line.
0: Underflow has not occurred
1: Underflow has occurred
Description
Rev. 6.00 Jun. 12, 2007 Page 267 of 610
REJ09B0131-0600