HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 634

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HD6417618

Manufacturer Part Number
HD6417618
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417618RBGN100V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Rev. 6.00 Jun. 12, 2007 Page 602 of 610
REJ09B0131-0600
Item
Figure 21.16 Synchronous
DRAM Single Read Bus Cycle
(Auto-Precharge,
CAS Latency = 2, WTRCD = 0
Cycle, WTRP = 0 Cycle)
Figure 21.17 Synchronous
DRAM Single Read Bus Cycle
(Auto-Precharge,
CAS Latency = 2, WTRCD = 1
Cycle, WTRP = 1 Cycle)
Figure 21.18 Synchronous
DRAM Burst Read Bus Cycle
(Single Read × 4)
(Auto-Precharge, CAS Latency =
2, WTRCD = 0 Cycle, WTRP = 1
Cycle)
Figure 21.19 Synchronous
DRAM Burst Read Bus Cycle
(Single Read × 4)
(Auto-Precharge, CAS Latency =
2, WTRCD = 1 Cycle, WTRP = 0
Cycle)
Figure 21.20 Synchronous
DRAM Single Write Bus Cycle
(Auto-Precharge, TRWL = 1
Cycle)
Figure 21.21 Synchronous
DRAM Single Write Bus Cycle
(Auto-Precharge, WTRCD = 2
Cycles, TRWL = 1 Cycle)
Figure 21.22 Synchronous
DRAM Burst Write Bus Cycle
(Single Write × 4)
(Auto-Precharge, WTRCD = 0
Cycle, TRWL = 1 Cycle)
Page Revision (See Manual for Details)
559
560
561
562
563
564
565
Amended
Amended
Amended
Amended
Amended
Amended
Amended
A25 to A0
A25 to A0
CKIO
CKIO
A25 to A0
A25 to A0
A25 to A0
CKIO
CKIO
CKIO
A25 to A0
CKIO
tAD1
t
AD1
Tr
Tr
tAD1
t
AD1
Tr
address
address
A25 to A0
Row address
tAD1
Row
Row
Row address
Tr
Trw
CKIO
Tr
address
tAD1
Row
t
AD1
TC1
Column
address
tAD1
Trw
Tr
t
Tc1
AD1
Column
address
tAD1
tAD1
Tc1
Tc1
Column
address
TC2
t
Column
address
Column address
AD1
tAD1
t
AD1
Row address
Tc2
address
Column
Tc1
Row address Column address
Trw
Tr
Column address
tAD1
tAD1
Td1
Tc4
Column
address
tAD1
Tcw
Tc2
Column
address
Td1
Tc3
Column
address
t
AD1
tAD1
Tcw
Tc1
Td2
Tc4
Trw
tAD1
tAD1
Td2
Tc4
Tc3
Column
address
Td1
Column
address
t
Td3
AD1
t
address
AD1
Column
Column address
Td3
Td1
Trwl
Tc1
tAD1
Tc4
Column
address
Td4
Tde
Td4
t
AD1
Tde
Trwl
Tde
tAD1
t
AD1
Tde
Trwl
tAD1
t
AD1
tAD1
Tap

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