HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 450

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface (HIF)
Rev. 6.00 Jun. 12, 2007 Page 418 of 610
REJ09B0131-0600
No.
9
10
11
12
13
14
Hereafter No. 12 to 14 are repeated. When a register other than HIFDATA is accessed (except
that HIFGSR read with HIFRS = low), HIFRAM consecutive read is interrupted, and No. 3 to 5
need to be done again.
CPU
External Device
DMAC
Consecutive
data read from
bank 1 in
HIFRAM
Read from end
address of bank
1 in HIFRAM
completes and
operation halts
Re-activate
DMAC
Consecutive
data read from
bank 0 in
HIFRAM
Read from end
address of bank
0 in HIFRAM
completes and
operation halts
Re-activate
DMAC
→ HIF bank
← Assert
→ HIF bank
← Assert
HIF
interrupt
occurs
HIFDREQ
interrupt
occurs
HIFDREQ
→ HIFRAM bank switching
← Set DTRG bit to 1
→ HIFRAM bank switching
← Set DTRG bit to 1
This LSI
CPU
Write data to bank 0 in
HIFRAM
by HIF bank interrupt
handler (external device
accesses bank 0 and on-
chip CPU accesses
bank 1)
Write data to bank 1 in
HIFRAM
by HIF bank interrupt
handler (external device
accesses bank 1 and on-
chip CPU accesses
bank 0)