HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 413

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

In receiving, the SCIF operates as follows:
1. The SCIF synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,
Figure 14.17 shows an example of SCIF receive operation.
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed
(overrun error is detected), further reception is prevented.
the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE
bit or REIE bit in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
Synchronization
Serial data
ORER
clock
RDF
Figure 14.17 Example of SCIF Receive Operation
interrupt
request
RXI
Bit 7
RDF flag cleared
interrupt handler
Data read from
Bit 0
LSB
SCFRDR and
to 0 by RXI
One frame
Section 14 Serial Communication Interface with FIFO (SCIF)
interrupt
request
MSB
Bit 7
RXI
Bit 0
Rev. 6.00 Jun. 12, 2007 Page 381 of 610
Bit 1
BRI interrupt request
Bit 6
by overrun error
Bit 7
REJ09B0131-0600