HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 449

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 15.5 Consecutive Read Procedure from HIFRAM by External DMAC
No.
12
13
Hereafter No. 11 to 13 are repeated. When a register other than HIFDATA is accessed (except
that HIFGSR read with HIFRS = low), HIFRAM consecutive write is interrupted, and No. 3 to 6
need to be done again.
No.
1
2
3
4
5
6
7
8
CPU
CPU
HIF initial setting
DMAC initial setting
Set HIFADR to
HIFRAM start
address
Set HIFRAM
consecutive read with
address increment in
HIFMCR
Select HIFDATA
External Device
External Device
DMAC
Write to end
address of bank
0 in HIFRAM
completes and
operation halts
Re-activate
DMAC
DMAC
Activate DMAC
→ HIF bank
← Assert
← Assert
HIF
interrupt
occurs
HIFDREQ
HIF
HIFDREQ
Rev. 6.00 Jun. 12, 2007 Page 417 of 610
→ HIFRAM bank switching
← Set DTRG bit to 1
← Set DTRG bit to 1
Section 15 Host Interface (HIF)
This LSI
This LSI
CPU
by HIF bank interrupt
handler (external device
accesses bank 1 and on-
chip CPU accesses
bank 0)
CPU
HIF initial setting
Write data to bank 1 in
HIFRAM
After writing data to end
address of bank 1 in
HIFRAM, perform
HIFRAM bank switching
(external device
accesses bank 1 and on-
chip CPU accesses
bank 0)
REJ09B0131-0600