HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 230

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Clock Pulse Generator (CPG)
Cautions:
1. The internal clock frequency is the product of the frequency of the CKIO pin and the
2. The peripheral clock frequency is the product of the frequency of the CKIO pin, the frequency
3. The PHY-LSI clock frequency is the product of the frequency of the CKIO pin, the frequency
4. ×1, ×1/2, or ×1/4 can be used as the division ratio of divider 1. Set the rate in the frequency
5. The division ratio of divider 2 is selected from ×1, ×1/2, or ×1/4 can be used as Set the rate in
6. The output frequency of PLL circuit 1 is the product of the frequency of the CKIO pin and the
7. The bus clock frequency is always set to be equal to the frequency of the CKIO pin.
8. The clock mode, the FRQCR register value, and the frequency of the input clock should be
8.4
The CPG has the following registers.
For details on the addresses of these registers and the states of these registers in each processing
state, see section 20, List of Registers.
• Frequency control register (FRQCR)
• PHY-LSI clock frequency control register (MCLKCR)
8.4.1
FRQCR is a 16-bit readable/writable register that specifies whether a clock is output from the
CKIO pin in standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency
division ratio of the peripheral clock. Only word access can be used on FRQCR.
FRQCR is initialized by a power-on reset due to the external input signal. However, it is not
initialized by a power-on reset due to a WDT overflow.
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frequency multiplication ratio of PLL circuit 1.
multiplication ratio of PLL circuit 1, and the division ratio of divider 1.
Do not set the peripheral clock frequency lower than the CKIO pin frequency.
multiplication ratio of PLL circuit 1, and the division ratio of divider 2.
control register.
the PHY-LSI clock frequency control register.
multiplication ratio of PLL circuit 1. It is set by the frequency control register.
decided to satisfy the range of operating frequency specified in section 21, Electrical
Characteristics, with referring to table 8.3.
Register Descriptions
Frequency Control Register (FRQCR)