HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 507

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.2.4
BARB is a 32-bit readable/writable register. BARB specifies the address used for a break
condition in channel B.
Bit
5
4
3
2
1
0
Bit
31 to 0
Break Address Register B (BARB)
Bit Name
IDA1
IDA0
RWA1
RWA0
SZA1
SZA0
Bit Name
BAB31 to
BAB 0
Initial
Value
0
0
0
0
0
0
Initial
Value
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Instruction Fetch/Data Access Select A
Select the instruction fetch cycle or data access cycle as
the bus cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
Read/Write Select A
Select the read cycle or write cycle as the bus cycle of the
channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
Operand Size Select A
Select the operand size of the bus cycle for the channel A
break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Description
Break Address B
Stores an address of LAB or IAB which specifies a break
condition in channel B.
data access cycle
Rev. 6.00 Jun. 12, 2007 Page 475 of 610
Section 18 User Break Controller (UBC)
REJ09B0131-0600