HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 403

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Receiving Serial Data (Asynchronous Mode):
Figures 14.7 and 14.8 show a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
No
No
Figure 14.7 Sample Flowchart for Receiving Serial Data
ER, DR, BRK or ORER = 1?
Read ER, DR, BRK flags in
Clear RE bit in SCSCR to 0
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Read receive data in
SCFSR and ORER
flag in SCFSR to 0
All data received?
Start of reception
End of reception
flag in SCLSR
RDF = 1?
No
Yes
Yes
Section 14 Serial Communication Interface with FIFO (SCIF)
Error handling
[1]
[2]
[3]
Yes
[1] Receive error handling and
[2] SCIF status check and receive
[3] Serial reception continuation
break detection:
flags in SCFSR, and the
ORER flag in SCLSR, to
identify any error, perform the
appropriate error handling,
then clear the DR, ER, BRK,
and ORER flags to 0. In the
case of a framing error, a
break can also be detected by
reading the value of the RxD
pin.
data read:
RDF = 1, then read the receive
data in SCFRDR, read 1 from
the RDF flag, and then clear
the RDF flag to 0. The
transition of the RDF flag from
0 to 1 can also be identified by
an RXI interrupt.
procedure:
read at least the receive
trigger set number of receive
data bytes from SCFRDR,
read 1 from the RDF flag, then
clear the RDF flag to 0. The
number of receive data bytes
in SCFRDR can be
ascertained by reading from
SCRFDR.
Read the DR, ER, and BRK
Read SCFSR and check that
To continue serial reception,
Rev. 6.00 Jun. 12, 2007 Page 371 of 610
REJ09B0131-0600