HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 515

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by
a power-on reset. Other bits are not initialized by a power-on reset. The four BRDR registers have
a queue structure and a stored register is shifted at every branch.
Bit
30 to 28
27 to 0
Bit
31
30 to 28
27 to 0
Bit Name
—
BSA27 to
BSA0
Bit Name
DVF
—
BDA27 to
BDA0
Initial
Value
All 0
Undefined
Initial
Value
0
All 0
Undefined
R/W
R
R
R
R/W
R
R
Description
Indicates whether or not the branch source address is
stored. When a branch is made, this flag is set to 1.
This flag is cleared to 0 by one of the following
conditions: when this flag is read from this register,
when PC trace is enabled, and when a power-on reset
is generated.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
These bits are always read as 0. The write value
should always be 0.
Store bits 27 to 0 of the branch destination address.
BRDR Valid Flag
Reserved
Branch Destination Address
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Branch Source Address
Store bits 27 to 0 of the branch source address.
Rev. 6.00 Jun. 12, 2007 Page 483 of 610
Section 18 User Break Controller (UBC)
REJ09B0131-0600