HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 161

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
10
9
8
7
6
5 to 2
1
0
Bit Name
WR3
WR2
WR1
WR0
WM

HW1
HW0
Initial
Value
1
0
1
0
0
All 0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
Number of Access Wait Cycles
Specify the number of wait cycles that are necessary for
read or write access.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 6.00 Jun. 12, 2007 Page 129 of 610
Section 7 Bus State Controller (BSC)
REJ09B0131-0600