HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 328

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Multi-Buffer Frame Receive Processing
If an error occurs during multi-buffer frame reception, the processing shown in figure 12.7 is
carried out by the E-DMAC.
Where the receive descriptor is shown as inactive (RACT bit = 0) in the figure, buffer data has
already been received normally, and where the receive descriptor is shown as active (RACT bit =
1), this indicates a buffer for which reception has not yet been performed. If a frame receive error
occurs in the first descriptor part where the RACT bit = 1 in the figure, reception is halted
immediately and a status write-back to the descriptor is performed.
If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register
(EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame
receive request, reception is continued from the buffer after that in which the error occurred.
Rev. 6.00 Jun. 12, 2007 Page 296 of 610
REJ09B0131-0600
E-DMAC
Inactivates RACT and writes RFE, RFS
Descriptor read
Figure 12.7 E-DMAC Operation after Receive Error
Write-back
R
A
C
T
0
0
0
1
1
1
1
1
1
R
D
E
L
0
0
0
0
0
0
0
0
1
Descriptors
R
F
P
1
1
0
0
0
0
0
0
0
0
R
F
P
0
0
0
0
1
0
0
0
0
0
Buffer
Start of frame
New frame reception
continues from buffer
Receive error
occurrence
Received data
Unreceived data