HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 333

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• Bit 19 (TFUF): Transmit FIFO underflow interrupt source bit in EESR may not be set.
• Bit 16 (RFOF): Receive FIFO overflow interrupt source bit in EESR may not be set.
• Bit 11 (CND), bit 10 (DLC), bit 9 (CD), bit 8 (TRO): The interrupt source bits in EESR for the
(2)
The following descriptions are of sample countermeasures for cases when software processing is
based on the frame transmit complete interrupt (bit 21 (TC) in EESR).
If the TC interrupt source bit (bit 21) in EESR is not set on completion of transmission, the system
will continue to wait for the TC interrupt, leading to stoppage of transmission. This situation arises
when the interrupt handler writes a 1 to clear the bit. The sample method given as case (a) below
takes the above possibility into account and avoids the problem by monitoring the transmit
descriptor in interrupt processing for interrupts other than the TC interrupt.
The sample method given as case (b) below avoids the above problem by setting a timeout limit
for retry processing when multiple transmit descriptors are in use.
Note: The countermeasure should be the one that best suits the structure of your driver and other
When this bit is used as an interrupt source but is not set when it should be, the software is not
notified of the interrupt. However, the upper layer will recognize the error in the form of an
underflow of the transmit FIFO.
Since the state of the interrupt source is written back to the relevant descriptor, check the
receive descriptor (RD0) to confirm the error status.
carrier not detected, loss of carrier detected, delayed collision detected, and transmit retry over
interrupts may not be set.
However, since the states of the interrupt sources are written back to the relevant descriptor,
check the transmit descriptor (TD0) to confirm the error status.
Example of a countermeasure when the software configuration is based on the frame
transmit complete interrupt
software.
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 6.00 Jun. 12, 2007 Page 301 of 610
REJ09B0131-0600