HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 528

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 User Debugging Interface (H-UDI)
19.3
The H-UDI has the following registers. For details on the addresses of these registers and the
states of these registers in each processing state, see section 20, List of Registers.
• Bypass register (SDBPR)
• Instruction register (SDIR)
• Boundary scan register (SDBSR)
• ID register (SDID)
19.3.1
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass
mode, SDBPR is connected between H-UDI pins (TDI and TDO). The initial value is undefined.
19.3.2
SDIR is a 16-bit read-only register. This register is in JTAG IDCODE in its initial state. It is
initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the H-
UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in
this register.
Rev. 6.00 Jun. 12, 2007 Page 496 of 610
REJ09B0131-0600
Bit
15 to 13
12
11 to 8
7 to 2
1
0
Register Descriptions
Bypass Register (SDBPR)
Instruction Register (SDIR)
Bit Name
TI7 to TI5
TI4
TI3 to TI0



Initial
Value
All 1
0
All 1
All 1
0
1
R/W
R
R
R
R
R
R
Description
Test Instruction 7 to 0
The H-UDI instruction is transferred to SDIR by a
serial input from TDI.
For commands, see table 19.2.
Reserved
These bits are always read as 1.
Reserved
This bit is always read as 0.
Reserved
This bit is always read as 1.