HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 368

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Serial Communication Interface with FIFO (SCIF)
Rev. 6.00 Jun. 12, 2007 Page 336 of 610
REJ09B0131-0600
Bit
4
3
2
Bit Name
RE
REIE

Initial
value
0
0
0
R/W
R/W
R
R
Description
Receive Enable
Enables or disables the SCIF serial receiver.
0:Receiver disabled*
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
Receive Error Interrupt Enable
Enables or disables the receive-error (ERI) interrupts
and break (BRI) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERI) and break interrupt
1: Receive-error interrupt (ERI) and break interrupt
Note: * ERI or BRI interrupt requests can be cleared
Reserved
This bit is always read as 0. The write value should
always be 0.
(BRI) requests are disabled*
(BRI) requests are enabled
2. Serial reception starts when a start bit is
by reading the ER, BR or ORER flag after it
has been set to 1, then clearing the flag to 0, or
by clearing RIE and REIE to 0. Even if RIE is
set to 0, when REIE is set to 1, ERI or BRI
interrupt requests are enabled.
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
detected in asynchronous mode, or
synchronous clock input is detected in
synchronous mode. Select the receive format
in SCSMR and SCFCR and reset the receive
FIFO before setting RE to 1.
1
2