HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 537

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

19.4.2
Table 19.4 Reset Configuration
Notes: 1. Selects to normal mode or ASE mode.
19.4.3
The timing of data output from the TDO differs according to the command type set in SDIR. The
timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,
SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.
When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are
set, the TDO signal is output at the TCK rising edge earlier than the JTAG standard by a half
cycle.
ASEMD*
High
Low
2. In ASE mode, the reset hold state is entered by driving the RES and TRST pins low for
1
Reset Configuration
TDO Output Timing
ASEMD0 = high: normal mode
ASEMD0 = low: ASE mode
the given time. In this state, the CPU does not start up, even if the RES pin is driven
high. After that, when the TRST pin is driven high, H-UDI operation is enabled, but the
CPU does not start up. The reset hold state is canceled by the following: another RES
assert (power-on reset) or TRST reassert.
RES
Low
High
Low
High
TRST
Low
High
Low
High
Low
High
Low
High
LSI State
Normal reset and H-UDI reset
Normal reset
H-UDI reset only
Normal operation
Reset hold*
Normal reset
H-UDI reset only
Normal operation
Section 19 User Debugging Interface (H-UDI)
Rev. 6.00 Jun. 12, 2007 Page 505 of 610
2
REJ09B0131-0600