HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 281

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the
4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is
11.4.2
The EtherC receiver separates the frame data (MII into preamble, SFD, DA (destination address),
SA (Source address), type/length, Data, and CRC data) and outputs DA, SA, type/length, Data to
the E-DMAC. Figure 11.3 shows the state transitions of the EtherC receiver.
transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the
carrier-not-detected state occurs during data transmission, these are reported as interrupt
sources.
more transmit data, continues transmitting.
Illegal carrier
Reception
detection
halted
Reset
[Legend]
SFD: Start frame delimiter
Note: * The error frame also transmits data to the buffer.
Reception
RE set
RE reset
Figure 11.3 EtherC Receiver State Transmissions
Idle
notification*
station destination address
Preamble
detection
Error
Promiscuous and other
Normal reception
Start of frame
reception
detection
Error
RX-DV negation
Receive error
detection
Receive error
detection
Rev. 6.00 Jun. 12, 2007 Page 249 of 610
Section 11 Ethernet Controller (EtherC)
Destination address
Wait for SFD
reception
reception
reception
reception
CRC
Data
reception
reception
Own destination address
or broadcast
or multicast
or promiscuous
End of
SFD
REJ09B0131-0600