HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 399

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 14.3 shows a sample flowchart for initializing the SCIF.
After reading BRK, DR, and ER flags
Clear TE and RE bits in SCSCR to 0
in SCFSR, and each flag in SCLSR,
Set TE and RE bits in SCSCR to 1,
Set data transfer format in SCSMR
Set RTRG1-0 and TTRG1-0 bits
in SCSCR (leaving TE, RE, TIE,
and set TIE, RIE, and REIE bits
in SCFCR, and clear TFRST
Set TFRST and RFRST bits
Set CKE1 and CKE0 bits
and RIE bits cleared to 0)
1-bit interval elapsed?
Figure 14.3 Sample Flowchart for SCIF Initialization
and RFRST bits to 0
write 0 to clear them
Set value in SCBRR
Start of initialization
End of initialization
in SCFCR to 1
Wait
Yes
Section 14 Serial Communication Interface with FIFO (SCIF)
No
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Wait at least one bit interval, then
set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits.
Setting the TE bit enables the TxD
and RxD pins to be used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
Rev. 6.00 Jun. 12, 2007 Page 367 of 610
REJ09B0131-0600