HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 282

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Ethernet Controller (EtherC)
1. When the receive enable (RE) bit is set, the receiver enters the receive idle state.
2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver
3. In normal mode, if the destination address matches the receiver’s own address, or if broadcast
4. Following data reception from the MII, the receiver carries out a CRC check. The result is
5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode
11.4.3
Each MII Frame timing is shown in figure 11.4.
Rev. 6.00 Jun. 12, 2007 Page 250 of 610
REJ09B0131-0600
TXD3 to TXD0
MII_TXD3 to
starts receive processing. Discards a frame with an invalid pattern.
or multicast transmission or promiscuous mode is specified, the receiver starts data reception.
indicated as a status bit in the descriptor after the frame data has been written to memory.
Reports an error status in the case of an abnormality.
register, the receiver prepares to receive the next frame.
MII_TXD0
TX-CLK
TX-CLK
TX-EN
TX-ER
TX-EN
TX-ER
CRS
COL
CRS
COL
MII Frame Timing
Figure 11.4 (1) MII Frame Transmit Timing (Normal Transmission)
Figure 11.4 (2) MII Frame Transmit Timing (Collision)
Preamble
Preamble
SFD
Data
JAM
CRC