HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 302

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.2.7
EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual
bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the
corresponding bit. In the initial state, interrupts are not enabled.
Rev. 6.00 Jun. 12, 2007 Page 270 of 610
REJ09B0131-0600
Bit
31
30
29 to 27
26
25
24
EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)
Bit Name

TWBIP

TABTIP
RABTIP
RFCOFIP
Initial
value
0
0
All 0
0
0
0
R/W
R
R/W
R
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Write-Back Complete Interrupt Permission
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Abort Detection Interrupt Permission
0: Transmit abort detection interrupt is disabled
1: Transmit abort detection interrupt is enabled
Receive Abort Detection Interrupt Permission
0: Receive abort detection interrupt is disabled
1: Receive abort detection interrupt is enabled
Receive Frame Counter Overflow Interrupt Permission
0: Receive frame counter overflow interrupt is disabled
1: Receive frame counter overflow interrupt is enabled