HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 235

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.5.2
The WDT will not count unless the multiplication ratio is changed simultaneously.
1. In the initial state, PFC2 to PFC0 = 011.
2. Set the desired values in bits PFC2 to PFC0 while the MDCHG bit in STBCR is 0. The values
3. The clock is immediately changed to the new division ratio.
Note: When the MDCHG bit in STBCR is set to 1, changing the FRQCR value has no effect on
8.5.3
The values of the mode control pins (MD2 to MD0) that define a clock operating mode are fetched
at a power-on reset and software standby while the MDCHG bit in STBCR is set to 1 register.
Even if changing the FRQCR with the MDCHG bit set to 1, the clock mode cannot immediately
be changed to the specified clock mode. This change can be reflected as a multiplication ratio or a
division ratio after leaving software standby mode to change operating modes. Reducing the PLL
settling time without changing again the multiplication ratio after the operating mode changing is
possible by the use of this.
The procedures for the mode change using software standby mode are described below.
1. Set bits MD2 to MD0 to the desired clock operating mode.
2. Set both the STBY and MDCHG bits in STBCR to 1.
3. Set the adequate value to the WDT so that the given oscillation settling time can be satisfied.
4. Set FRQCR to the desired mode. Set bits STC2 to STC0 to the desired multiplication ratio. At
5. Enter software standby mode using the SLEEP instruction.
6. Leave software standby mode using an interrupt.
7. After leaving software standby mode, this LSI starts the operation with the value of FRQCR
that can be set are limited by the clock mode and the multiplication ratio of PLL circuit 1. Note
that if the wrong value is set, this LSI will malfunction.
Then stop the WDT.
this time, a division ratio can be set in bits PFC2 to PFC0. During the operation before the
mode change, the clock cannot be changed to the specified clock.
that has been set before the mode change.
the operation immediately. For details, see section 8.5.3, Changing Clock Operating
Mode.
Changing Division Ratio
Changing Clock Operating Mode
Rev. 6.00 Jun. 12, 2007 Page 203 of 610
Section 8 Clock Pulse Generator (CPG)
REJ09B0131-0600