HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 309

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.2.11 FIFO Depth Register (FDR)
FDR is a 32-bit readable/writable register that specifies the capacity of the transmit and receive
FIFOs.
Bit
31 to 11
10 to 8
7 to 3
2 to 0
Bit Name

TFD2 to
TFD0

RFD2 to
RFD0
Initial
value
All 0
B’000
All 0
B’000
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R
R
R/W
R
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Specify the capacity of transmit FIFO. The set value
should not be changed after the transmit/receive
operation is started.
000: 256 bytes
001: 512 bytes (Setting prohibited in SH7618,
Other than above: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive FIFO Capacity
Specify the capacity of receive FIFO. The set value
should not be changed after the transmit/receive
operation is started.
000: 256 bytes
001: 512 bytes (Setting prohibited in SH7618,
Other than above: Setting prohibited
Description
Transmit FIFO Capacity
setting enabled in SH7618A)
setting enabled in SH7618A)
Rev. 6.00 Jun. 12, 2007 Page 277 of 610
REJ09B0131-0600