HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 179

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

When buffers are placed on the data bus, the RD signal should be used to control the buffers. The
RD/WR signal indicates the same state as a read cycle (driven high) when no access has been
carried out. Therefore, care must be taken when controlling the buffers with the RD/WR signal, to
avoid data conflict.
Figures 7.4 and 7.5 show the basic timings of normal space consecutive access. If the WM bit in
CSnWCR is cleared to 0, a Tnop cycle is inserted to check the external wait (figure 7.4). If the
WM bit in CSnWCR is set to 1, an external wait request is ignored and no Tnop cycle is inserted
(figure 7.5).
Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 bits,
Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0)
Read
Write
A25 to A0
D15 to D0
WEn(BEn)
D15 to D0
RD/WR
CKIO
WAIT
CSn
RD
BS
T1
T2
Tnop
Rev. 6.00 Jun. 12, 2007 Page 147 of 610
Section 7 Bus State Controller (BSC)
T1
T2
REJ09B0131-0600