HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 311

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.2.13 E-DMAC Operation Control Register (EDOCR)
EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC
operation.
Bit
31 to 4
3
2
1
0
Bit Name

FEC
AEC
EDH

Initial
value
All 0
0
0
0
0
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R
R/W
R
R/W
R/W
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
FIFO Error Control
Specifies E-DMAC operation when transmit FIFO
underflow or receive FIFO overflow occurs.
0: E-DMAC operation continues when underflow or
1: E-DMAC operation halts when underflow or
Address Error Control
Indicates detection of an illegal memory address in an
attempted E-DMAC transfer.
0: Illegal memory address not detected (normal
1: E-DMAC stops its operation due to illegal memory
Note: To resume the operation, set the E-DMAC
E-DMAC Halted
0: The E-DMAC is operating normally
1: The E-DMAC has been halted by NMI pin
Reserved
This bit is always read as 0. The write value should
always be 0.
Description
overflow occurs
overflow occurs
operation)
address detection
assertion. E-DMAC operation is restarted by
writing 0
again after software reset by means of the
SWR bit in EDMR.
Rev. 6.00 Jun. 12, 2007 Page 279 of 610
REJ09B0131-0600