HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 256
HD6417618
Manufacturer Part Number
HD6417618
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417618.pdf
(646 pages)
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Section 10 Power-Down Modes
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT.
2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to
appropriate values to secure the specified oscillation settling time.
3. After setting the STBY bit in STBCR to 1, execute the SLEEP instruction.
4. Software standby mode is entered and the clocks within this LSI are halted.
10.5.2
Canceling Software Standby Mode
Software standby mode is canceled by interrupts (NMI, IRQ) or a reset.
Canceling with Interrupt: The WDT can be used for hot starts. When an NMI or IRQ interrupt is
detected, the clock will be supplied to the entire LSI and software standby mode will be canceled
after the time set in the timer control/status register of the WDT has elapsed. Interrupt exception
handling is then executed. After the branch to the interrupt handling routine, clear the STBY bit in
STBCR. WTCNT stops automatically. If the STBY bit is not cleared, WTCNT continues
operation and a transition is made to software standby mode* when it reaches H'80. This function
prevents data destruction due to the voltage rise by an unstable power supply voltage.
IRQ cancels the software standby mode when the input condition matches the specified detect
condition while the IRQn1S and IRQn0S bits in IRQCR are not B'00 (settings other than the low
level detection). When the priority level of an IRQ interrupt is lower than the interrupt mask level
set in the status register (SR) of the CPU, the execution of the instruction following the SLEEP
instruction starts again after the cancellation of software standby mode. When the priority level of
an IRQ interrupt is higher than the interrupt mask level set in the status register (SR) of the CPU,
IRQ interrupt exception handling is executed after the cancellation of software standby mode.
Note: * This software standby mode can be canceled only by a power-on reset.
Rev. 6.00 Jun. 12, 2007 Page 224 of 610
REJ09B0131-0600
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