HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 11

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

3.4
Section 4 U Memory..............................................................................................63
4.1
4.2
Section 5 Exception Handling ...............................................................................65
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
3.3.3
3.3.4
3.3.5
Memory-Mapped Cache ...................................................................................................... 58
3.4.1
3.4.2
3.4.3
Features................................................................................................................................ 63
Usage Notes ......................................................................................................................... 63
Overview.............................................................................................................................. 65
5.1.1
5.1.2
5.1.3
Resets ................................................................................................................................... 69
5.2.1
5.2.2
5.2.3
Address Errors ..................................................................................................................... 71
5.3.1
5.3.2
Interrupts.............................................................................................................................. 72
5.4.1
5.4.2
5.4.3
Exceptions Triggered by Instructions .................................................................................. 74
5.5.1
5.5.2
5.5.3
5.5.4
Cases when Exceptions are Accepted .................................................................................. 76
Stack States after Exception Handling Ends ........................................................................ 77
Usage Notes ......................................................................................................................... 79
5.8.1
5.8.2
5.8.3
5.8.4
Write Access ........................................................................................................... 56
Write-Back Buffer .................................................................................................. 57
Coherency of Cache and External Memory ............................................................ 57
Address Array ......................................................................................................... 58
Data Array .............................................................................................................. 59
Usage Examples...................................................................................................... 61
Types of Exception Handling and Priority.............................................................. 65
Exception Handling Operations .............................................................................. 66
Exception Handling Vector Table........................................................................... 67
Types of Resets....................................................................................................... 69
Power-On Reset ...................................................................................................... 69
H-UDI Reset ........................................................................................................... 70
Address Error Sources ............................................................................................ 71
Address Error Exception Source............................................................................. 71
Interrupt Sources..................................................................................................... 72
Interrupt Priority ..................................................................................................... 73
Interrupt Exception Handling ................................................................................. 73
Types of Exceptions Triggered by Instructions ...................................................... 74
Trap Instructions ..................................................................................................... 74
Illegal Slot Instructions ........................................................................................... 75
General Illegal Instructions..................................................................................... 75
Value of Stack Pointer (SP) .................................................................................... 79
Value of Vector Base Register (VBR) .................................................................... 79
Address Errors Caused by Stacking for Address Error Exception Handling .......... 79
Notes on Slot Illegal Instruction Exception Handling ............................................ 79
Rev. 6.00 Jun. 12, 2007 Page xi of xxxii