TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 99

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.6
3.6.1
Chip Select/Wait Controller
bus width and the number of waits can be set independently for each address area (
and others).
output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas,
the corresponding
(in ROM or SRAM). However, in order for the chip select signal to be output, the port 6 function
register (P6FC) must be set.
CS/WAIT controller.
MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3.
master enable/disable status the data bus width and the number of waits for each address area.
On the TMP91C820A, four user-specifiable address areas (
The pins
These pins are
The areas CS0 to CS3 are defined by the values in the memory start address registers
The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the
The input pin controlling these states is the bus wait request pin (
CS2A
Specifying an Address Area
MSAR3) and memory address mask registers (MAMR0 to MAMR3).
specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this
indicates an access to the corresponding CS area. In this case, the
the chip select signal and the bus cycle operates in accordance with the settings in chip
select/wait control register B0CS to B3CS. (See 3.6.2 “Chip Select/Wait Control Registers”.)
The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to
At each bus cycle, a compare operation is performed to determine if the address on the
to
CS2G
CS0
to
and
CS
CS0
CS3
pin that area and BANK value is fixed without concern in setting of
CSEXA
to
(which can also function as port pins P60 to P63) are the respective
CS3
(CS pin except
pin outputs the chip select signal for the specified address area
91C820A-97
CS0
to
CS3
) are made by MMU.
CS0
to
WAIT
CS3
CS0
) can be set. The data
).
to
CS3
TMP91C820A
2008-02-20
CS0
pin outputs
to
CS3