TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 186

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

SDA line
SCL line
Start condition
(6) Transmitter/receiver selection
(7) Start/stop condition generation
Figure 3.10.9 Start Condition Generation and Slave Address Generation
the <TRX> to 0 for operation as a receiver. When data with an addressing format is
transferred in slave mode, when a slave address with the same value that an I2C0AR
or a GENERAL CALL is received (All 8-bit data are 0 after a start condition), the
<TRX> is set to 1 by the hardware if the direction bit (R/
device is 1, and is cleared to 0 by the hardware if the bit is 0. In the master mode, after
an acknowledge signal is returned from the slave device, the <TRX> is cleared to 0 by
the hardware if a transmitted direction bit is 1, and is set to 1 by the hardware if it is 0.
When an acknowledge signal is not returned, the current condition is maintained.
detected or arbitration is lost.
SBI0DBR are output on a bus after generating a start condition by writing 1 to the
SBI0CR2 <MST, TRX, BB, PIN>. It is necessary to set transmitted data to the data
buffer register (SBI0DBR) and set 1 to <ACK> beforehand.
to the <MST, TRX, PIN>, and 0 to the <BB>. Do not modify the contents of <MST, TRX,
BB, and PIN> until a stop condition is generated on a bus.
SBI0SR<BB> will be set to 1 if a start condition has been detected on the bus, and will
be cleared to 0 if a stop condition has been detected.
point. Please refer to 3.10.6 (4) “Stop condition generation”.
Set the SBI0CR2<TRX> to 1 for operating the TMP91C820A as a transmitter. Clear
The <TRX> is cleared to 0 by the hardware after a stop condition on the I
When the SBI0SR<BB> is 0, slave address and direction bit which are set to
When the <BB> is 1, a sequence of generating a stop condition is started by writing 1
The state of the bus can be ascertained by reading the contents of SBI0SR<BB>.
And about generation of stop condition in master mode, there are some limitation
A6
1
Figure 3.10.10 Stop Condition Generation
SDA line
SCL line
A5
2
Slave address and the direction bit
A4
3
91C820A-184
A3
4
Stop condition
A2
5
A1
6
A0
7
W
R/
) sent from the master
W
8
Acknowledge
signal
TMP91C820A
9
2008-02-20
2
C bus is