TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 180

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

SBI0CR1
Prohibit
read-
modify-
write
Note 1: Set the <BC2:0> to 000 before switching to a clock synchronous 8-bit SIO mode.
Note 2: For the frequency of the SCL line clock, see 3.10.5 (3) “Serial clock”.
Note 3: Initial data of SCK0 is “0”, SWRMON is “1”.
Note 4: This I
(0240H)
3.10.4
allows the setting of a baud rate over 100 kbps, the compliance with the I
case.
Bit symbol
Read/Write
After Reset
Function
2
C bus circuit dose not support fast mode, it supports standard mode only. Although the I
I
the serial bus interface (SBI) in the I
2
C Bus Mode Control
The following registers are used to control and monitor the operation status when using
Number of transferred bits
(Note 1)
BC2
7
0
Figure 3.10.3 Registers for the I
BC1
W
6
0
Seirial Bus Interface Conrol Register 1
BC0
5
0
91C820A-178
Acknowledge
mode
specification
0: Not
1: Generate
2
C bus mode.
generate
ACK
R/W
4
0
Internal serial clock selection <SCK2:0> at write
Software reset state monitor <SWRMON> at read
Acknowledge mode specification
Number of bits transferred
000
001
010
011
100
101
110
111
<BC2:0>
0
1
0
1
000
001
010
011
100
101
110
111
n = 10
n = 11
n = 5
n = 6
n = 7
n = 8
n = 9
2
C Bus Mode
During software reset
Initial data
Not generate clock pulse for acknowledge signal
Generate clock pulse for acknowledge signal
3
clock pulses
2
Number of
− (Note4)
− (Note4)
− (Note4)
− (Note4)
69.2
34.9
17.5
(Reserved)
C specification is not guaranteed in that
8
1
2
3
4
5
6
7
<ACK> = 0
Internal serial clock selection and
software reset monitor
(Note 2)
SCK2
kHz
kHz
kHz
2
0
Bits
W
8
1
2
3
4
5
6
7
System clock: fc
Clock gear: fc/1
fc = 36 MHz
(Internal SCL output)
fscl =
SCK1
2
1
0
C bus circuit itself
Number of
2
n
pulses
fc
clock
+ 8
9
2
3
4
5
6
7
8
0/1 (Note 3)
TMP91C820A
<ACK> = 1
SWRMON
SCK0/
[ Hz ]
R/W
2008-02-20
0
Bits
8
1
2
3
4
5
6
7