TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 43

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.4
Interrupts
interrupt controller.
the CPU. If multiple interrupts are generated simultaneously,the interrupt controller sends the
interrupt with the highest priority to the CPU. (The highest priority possible is level 7, used for
non-maskable interrupts.)
mask register <IFF2:0>. If the priority level of the interrupt is higher than the value of the
interrupt mask register, the CPU accepts the interrupt.
processed without comparison with the <IFF2:0> value.
instruction (Executing EI num sets the content of <IFF2:0> to num). For example, specifying
EI3 enables the acceptance of maskable interrupts whose priority level set in the interrupt
controller is 3 or higher, and enables the acceptance of non-maskable interrupts. However, if EI
or EI0 is specified, maskable interrupts with a priority level of 1 or higher and non-maskable
interrupts are accepted (Operationally identical to “EI” 1).
the priority level of maskable interrupts is 1 to 6, the DI instruction is used to dasable maskable
interrupt. The EI instruction is vaild immediately after execution begins. (With TLCS-90, the
EI instruction is vaild after execution of the instruction following the EI insutruction.)
interrupts have a micro DMA processing mode as well.
mode, this mode can be used for speeding up interrupt processing, such as transferring data to
I/O. TMP91C820A also has a micro DMA soft start function for requesting micro DMA
processing by software not by interrupt.
Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in
The TMP91C820A has a total of 43 interrupts divided into the following 5 types:
A (Fixed) individual interrupt vector number is assigned to each interrupt.
One of six (Variable) priority levels can be assigned to each maskable interrupt.
The priority level of non-maskable interrupts is fixed at 7, the highest level.
When an interrupt is generated, the interrupt controller sends the piority of that interrupt to
The CPU compares the priority level of the interrupt with the value of the CPU interrupt
However, software interrupts and illegal instruction interrupts generated by the CPU are
The interrupt mask register <IFF2:0> value can be updated using the value of the EI
Operationally, the DI instruction (<IFF2:0> is 7) is identical to the EI 7 instruction, but as
In addition to the general-purpose interrupt processing mode described above, TLCS-900/L1
Because the CPU transfers (Byte transfer, or 4-byte transfer) automatically in micro DMA
Figure 3.4.1 shows the overall interrupt processing flow.
•
•
•
Interrupts generated by CPU: 9 sources
(Software interrupts, illegal instruction interrupt)
Internal interrupts: 28 sources
Interrupts on external pins (
91C820A-41
NMI
and INT0 to INT3, INTKEY): 6 sources
TMP91C820A
2008-02-20