TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet
TMP91xy20AFG
Specifications of TMP91xy20AFG
Related parts for TMP91xy20AFG
TMP91xy20AFG Summary of contents
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... TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C820AFG Semiconductor Company ...
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... Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • ...
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Built-in RAM: 8 Kbytes Built-in ROM: 8 Kbytes (However, 9999 (ROM code) has no internal ROM.) (4) External memory expansion • Expandable up to 136 Mbytes (Shared program/data area) • Can simultaneously support 8- or 16-bit width external data ...
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... Clock gear function: Select a high-frequency clock fc to fc/16 RTC (fs = 32.768 kHz) (23) Operating voltage • VCC = 2 3 MHz) • VCC = 3 3.6 V (fc max = 36 MHz) (24) Package • 144-pin QFP: LQFP144-P-1616-0.40C • Chip form supply also available. For details, contact your local Toshiba sales representative. 91C820A-3 TMP91C820A 2008-02-20 ...
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ADTRG AN0 to AN7 10-bit 8ch (P80 to P87) AD converter AVCC, AVSS VREFH, VREFL TXD0 (PC0) SIO/UART/IrDA RXD0 (PC1) (SIO0) SCLK0/ (PC2) CTS0 TXD1 (PC3) SIO/UART RXD1 (PC4) (SIO1) SCLK1/ (PC5) CTS1 OPTRX0, SCK (P70) Serial bus (P71) ...
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Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91C820A, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C820AFG. 1 P81/AN1 P82/AN2 P83/AN3/ ADTRG P84/AN4 ...
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PAD layout (Chip size 5.75 mm × 5.63 mm) PIN Name X Point Y Point No. −2742 1 P81 2128 −2742 2 P82 2004 −2742 3 P83 1888 −2742 4 P84 1774 −2742 5 P85 1660 −2742 6 P86 ...
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Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.3.1 Pin Names and Functions (1/4) Number Pin Name I/O of Pins P00 to P07 8 I I/O P10 ...
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Table 2.3.2 Pin Names and Functions (2/4) Number Pin Name I/O of Pins P70 1 I/O SCK I/O OPTRX0 Input P71 1 I/O S0 Output SDA I/O OPTRX0 Output P72 1 I/O SI Input SCL I/O P73 1 I/O Output ...
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Table 2.3.3 Pin Names and Functions (3/4) Number Pin Name I/O of Pins PB5 1 I/O INT2 Input TA3OUT Output PB6 1 I/O INT3 Input TB0OUT0 Outout PC0 1 I/O TXD0 Output PC1 1 I/O RXD0 Input PC2 1 I/O ...
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Table 2.3.4 Pin Names and Functions (4/4) Number Pin Name I/O of Pins PF2 1 Output Output SDWE PF3 1 Output SDLDQM Output PF4 1 Output SDUDQM Output PF5 1 Output SDCKE Output PF6 1 Output SDCLK Output PF7 1 ...
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Operation This following describes block by block the functions and operation of the TMP91C820A. Notes and restrictions for eatch book are outlined in 6 “Points of Note and Restrictions” at the end of this manual. 3.1 CPU The TMP91C820A ...
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Read Figure 3.1.1 TMP91C820A-9999 Reset Timing Example (The case of using external ROM) 91C820A-12 TMP91C820A Write 2008-02-20 ...
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Memory Map Figure 3.2 memory map of the TMP91C820A. 000000H Internal I/O (4 Kbytes) 000100H 000FE0H 001000H Internal RAM (8 Kbytes) 003000H 010000H External memory FFE000H Mask ROM (8 FFFF00H Vector table (256 bytes) FFFFFFH Note: Address ...
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Triple Clock Function and Standby Function TMP91C820A contains (1) Clock gear, (2) Clock doubler (DFM), (3) Standby controller, and (4) Noise-reducing circuit used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of ...
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The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (The X1, X2, XT1 and XT2 pins and DFM). Figure ...
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Block Diagram of System Clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> DFMCR0<ACT1:0, DLUPTM> Warm-up timer (High-/low-frequency oscillator), lockup timer (DFM) SYSCR0 <XTEN, RXTEN> XT1 Low-frequency fs oscillator XT2 = f f DFM OSCH SYSCR0 <XEN, RXEN> Clock doubler (DFM) X1 High-frequency oscillator X2 ...
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SFRs 7 6 SYSCR0 Bit symbol XEN XTEN (00E0H) Read/Write After reset 1 1 High- Low- Function frequency frequency oscillator (fc) oscillator (fs) 0: Stop 0: Stop 1: Oscillation 1: Oscillation (Note Bit symbol SYSCR1 (00E1H) ...
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Symbol Name Address 7 ACT1 R/W 0 DFM DFM DFMCR0 control E8H 00 STOP STOP register 0 01 RUN RUN 10 RUN STOP 11 RUN STOP D7 DFM R/W DFMCR1 control E9H 0 register 1 Limitation point on the use ...
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Bit symbol PROTECT TA3LCDE EMCCR0 Read/Write R R/W (00E3H) After reset 0 0 Function Protect flag LCDC 0: OFF Source clock kHz 1: TA3OUT Bit symbol EMCCR1 Read/Write (00E4H) After reset Switching the protect ...
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System Clock Controller The system clock controller generates the system clock signal (f internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc ...
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Example 1: Setting the clock Changing from high frequency (fc) to low frequency (fs). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H (SYSCR2), −X11− − − −B LD SET 6, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) JR ...
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Example 2: Setting the clock Changing from low frequency (fs) to high frequency (fc). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H (SYSCR2), − X10 − − − − SET 7, (SYSCR0) SET 2, (SYSCR0) WUP: BIT ...
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Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> set according to the contents of the clock gear select register SYSCR1<GEAR0:2> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the ...
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Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1,SBI) there is a prescaler which can divide the clock. The φ T clock input to the prescaler is either the clock f divided by 2. The ...
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Limitation point on the use of DFM 1. It’s prohibited to execute DFM enable/disable control in the SLOW mode (fs) (Write to DFMCR0<ACT1:0> = “10”). You should control DFM in the NORMAL mode you stop DFM operation during ...
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Change/stop control (OK) DFM use mode (f ) → High-frequency oscillator operation mode (f DFM DFM stop → Low-frequency oscillator operation mode (fs) → High-frequency oscillator stop (DFMCR0), 11 − − − − − − (DFMCR0), 00 ...
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Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) Runaway provision with SFR protection ...
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Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Resonator C2 XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to ...
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Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that the state which is fetch ...
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Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When writes operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. ...
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Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: ...
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How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT modes. ...
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Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT mode NMI INTWDT INT0 to INT3 (Note 1) INTALM0 to INTALM4 INTTA0 to INTTA3, INTTB00 to INTTB01 INTRX0 to INTRX2, TX0 to TX2 INTSS0 ...
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Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of ...
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STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<SELDRV, DRVE> register. Table 3.3.6, Table 3.3.7 summarizes the state of these pins ...
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The STOP mode is entered when the low frequency operates, and high frequency operates after releasing due to NMI. Address SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H 8FFDH LD (SYSCR1), 08H (SYSCR2), − X1001X1B 9000H LD ...
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Table 3.3.6 Input buffer state table (1/2) When the CPU is Input operating Port Function During When Name Name Reset Used as function Pin P00-P07 D0-D7 OFF 8bit start: ON upon OFF external 16bit start: read P10-P17 D8-D15 ON Built-in ...
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When the CPU is Input operating Port Function During When Name Name Reset Used as function Pin PB0 TA0IN PB1 RXD2 PB3 INT0 ON PB4 INT1 PB5 INT2 PB6 INT3 − − PC0 PC1 RXD0 ON SCLK0, PC2 CTS0 − ...
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Table 3.3.7 Output buffer state table (1/2) When the CPU is Output operating Port Function During When Name Name Reset Used as function Pin P00-P07 D0-D7 ON upon OFF external P10-P17 D8-D15 read P20-P27 A16-A23 8bit start: ON P30-P37 A8-A15 ...
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When the CPU is Output operating Port Function During When Name Name Reset Used as function Pin PB0 TXD2 ON PB1 TA1OUT − PB3 − − PB4 PB5 TA3OUT ON PB6 TB0OUT0 OFF PC0 TXD0 − − PC1 PC2 SCLK0 ...
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Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C820A has a total of 43 interrupts divided into the following 5 types: • Interrupts generated by CPU: 9 sources (Software ...
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Interrupt processing Interrupt specified by micro DMA start vector? No Interrupt vector value “V” read Interrupt request F/F clear General-purpose PUSH PC interrupt PUSH SR processing SR<IFF2:0>← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 PC ← ...
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General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps a and c ...
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Table 3.4.1 TMP91C820A Interrupt Vectors and Micro DMA Start Vectors Default Interrupt Source and Source of Micro DMA Type Priority 1 “Reset” or “SWI0” instruction 2 “SWI1” instruction 3 INTUNDEF: Illegal instruction or “SWI2” instruction 4 “SWI3” instruction 5 “SWI4” ...
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Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C820A supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level for maskable interrupts (Level 6), regardless of the ...
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While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (The upper 8 bits of the 32 bits are not ...
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Soft start function In addition to starting the micro DMA function by interrupts, TMP91C820A includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to ...
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Detailed description of the transfer mode register 8 bits DMAM0 Mode DMAM3 Number of Transfer Bytes 000 000 Transfer destination address INC mode 00 Byte transfer (Fixed) ................................................. I/O to memory (DMADn+) ← (DMASn) DMACn ...
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Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. ...
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Figure 3.4.3 Block Diagram of Interrupt Controller 91C820A-50 TMP91C820A 2008-02-20 ...
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Interrupt level setting registers Symbol Name Address 7 INT0 and IADC INTE0AD INTAD 90H R enable 0 INT1 and I2C INTE12 INT2 91H R enable 0 INT3 and IA4C INTE3ALM4 INTALM4 92H R enable 0 INTALM0 IA1C and INTEALM01 ...
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Symbol Name Address 7 INTRX1 ITXT1C and INTES1 99H INTTX1 R enable 0 INTSBI ILCD1C and INTES2LCD 9AH INTLCD R enable 0 INTTC0 ITC1C and INTETC01 9BH INTTC1 R enable 0 INTTC2 ITC3C and INTETC23 9CH INTTC3 R enable 0 ...
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External interrupt control Symbol Name Address 7 − 8CH 0 Interrupt Always IIMC input mode write “0”. control (Prohibit RMW) INT0 level enable 0 edge detect INT 1 H level INT rising edge enable NMI 0 INT request generation ...
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Symbol Name Address 7 DMA0 DMA0V start 80H vector DMA1 DMA1V start 81H vector DMA2 DMA2V start 82H vector DMA3 DMA3V start 83H vector (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until ...
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Notes The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute ...
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Port Functions The TMP91C820A features 126-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 ...
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Table 3.5.2 Port Functions (2/2) Number of Port Name Pin Name Pins Port D PD0 1 PD1 1 PD2 1 PD3 1 PD4 1 PD6 1 PD7 1 Port E PD0 to PD7 8 Port F PF0 1 PF1 1 ...
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Table 3.5.3 I/O Registers and Specifications (1/3) Port Pin Name Specification Port 0 P00 to P07 Input port Output port bus Port 1 P10 to P17 Input port Output port D8 to D15 bus Port 2 P20 ...
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Table 3.5.4 I/O Registers and Specifications (2/3) Port Pin Name Specification Port 7 P70 to P77 Input port Output port P70 SCK input SCK output OPTRX0 input P71 SDA input SDA output SO output OPTTX0 output P72 SI input SCL ...
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Table 3.5.5 I/O Registers and Specifications (3/3) Port Pin Name Port C PC0 to PC5 Input port Output port PC0 TXD0 output PC1 RXD0 input PC2 SCLK0 input SCLK0 output input CTS0 PC3 TXD1 output PC4 RXD1 input PC5 SCLK1 ...
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Port 0 (P00 to P07) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P0CR. Resetting resets all bits of the output latch P0, the control ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR and the function register P1FC. Resetting resets all bits of the ...
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P0 P1 Bit symbol P17 P16 (0000H) (0001H) Read/Write After reset Data from external port (Output latch register is cleared to 0 P1CR Bit symbol P17C P16C (0004H) Read/Write After reset 0 0 Function 7 6 ...
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Port 2 (P20 to P27) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P2CR and the function register P2FC. In addition to functioning as a ...
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P0 P2 Bit symbol P27 P26 (0006H) (0000H) Read/Write After reset Data from external port (Output latch register is cleared to 0 P2CR Bit symbol P27C P26C (0008H) Read/Write After reset 0/1 0/1 (Note3) Function 7 ...
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Port 3 (P30 to P37) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P3CR and the function register P3FC. In addition to functioning as a ...
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P0 P3 Bit symbol P37 P36 (0007H) (0000H) Read/Write After reset Data from external port (Output latch register is cleared to 0 P3CR Bit symbol P37C P36C (000AH) Read/Write After reset 0/1 0/1 (Note3) Function 7 ...
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Port 4 (P40 to P47) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P4CR and the function register P4FC. In addition to functioning as a ...
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P0 P4 Bit symbol P47 P46 (000CH) (0000H) Read/Write After reset Data from external port (Output latch register is cleared to 0 P4CR Bit symbol P47C P46C (000EH) Read/Write After reset 0/1 0/1 (Note3) Function 7 ...
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Port Z (PZ0 to PZ3) Port 4-bit general-purpose I/O port (P50 and P51 are used for output only). I/O is set using control register PZCR and PZFC. Resetting resets all bits of the output latch PZ ...
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Reset Function control (on bit basis) PZFC write S A Output latch B PZ write Output buffer PZ read WR Internal address area Reset Direction control (on bit basis) PZCR write Function conrtol (on bit basis) PZFC write S S ...
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Reset Direction control (on bit basis) PZCR write Function conrtol (on bit basis) PZFC write Output latch B Output buffer C PZ write SRWE P5 read Figure 3.5.13 Port Z (PZ3) 91C820A-72 TMP91C820A (Programmable ...
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PZ Bit symbol (007DH) Read/Write After reset Function 7 6 PZCR Bit symbol (007EH) Read/Write After reset Function 7 6 Bit symbol PZFC (007FH) Read/Write After reset Function Note 1: Output latch register is set ...
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Port 5 (P56) Port 1-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to P1. In addition to functioning as a general-purpose I/O ...
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P5 Bit symbol P56 (000DH) Read/Write R/W After reset Data from external port (Output latch register is set to 1.) Function 0(Output latch register): Pull-up resistor OFF 1(Output latch register): Pull-up resistor P5CR Bit symbol ...
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Port 6 (P60 to P67) Port are 8-bit output ports. Resetting sets output latch of P62 to 0 and output latches of P60 to P61 and P63 to P67 are set to 1. Port 6 also ...
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Port 7 (P70 to P77) Port 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets port 7 to input port and all bits of output latch to 1. ...
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Port 71 (SO/SDA/OPTTX0) Port general-purpose I/O port also used as SDA (Data input for I mode), SO (Data output for SIO mode) for serial bus interface and OPTTX0 (Transmit output for IrDA mode of ...
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Port 72 (SI/SCL) Port general-purpose I/O port also used as SI (Data input for SIO mode), SCL (Clock input/output for I C bus mode) for serial bus interface. 2 Reset Direction control (on bit ...
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Port CS2F CS2G Port are general-purpose I/O ports. These are also used as control signal for sequential mask ROM and extend chip-select output. Reset Function control 2 (on ...
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Port 76 (MSK), 77 (VEECLK) Port 76 and 77 are general-purpose I/O ports. These are also used as clock control function for voltage booster of external LCD driver. MSK pin (P76 input pin from external LCD driver, ...
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P7 Bit symbol P77 P76 (0013H) Read/Write After reset 7 6 P7CR Bit symbol P77C P76C (0016H) Read/Write After reset 0 0 Function 7 6 Bit symbol P77F P76F P7FC (0017H) Read/Write After reset Function 0:Port MSK 1:VEECLK ...
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Port 8 (P80 to P87) Port 8-bit input port and can also be used as the analog input pins for the internal AD converter. P83 can also be used as ADTRG pin for the AD converter. ...
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Port 9 (P90 to P97) Port are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O port, port can also key-on wakeup function as keyboard interface. The various functions ...
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Port A (PA0 to PA7) Port PA0 to PA7 are 8-bit output ports, and also used key board interface pin KO0 to KO7 which can set open-drain output buffer. Writing 1 in the corresponding bit of the port A ...
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Port B (PB0 to PB6) Port 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port input port. In addition to functioning as a general-purpose ...
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PB1 (TA1OUT, RXD2) Port B1 is I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD2 possible to logical invert by setting the register PB<PB1>. Reset Direction ...
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PB4 (INT1), PB5 (INT2, TA3OUT), PB6 (INT3, TB0OUT0) Reset Direction control (on bits basis) PBCR write Function control (on bit basis) PBFC write S Output latch PB write PB read INT1 edge detection Reset Direction control (on bits basis) ...
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PB Bit symbol PB6 (0022H) Read/Write After reset − Function 7 6 PBCR Bit symbol PB6C (0024H) Read/Write After reset 0 Function 7 6 Bit symbol PB6F PBFC (0025H) Read/Write After reset 0 Function 0: Port 1: INT3 ...
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Port C (PC0 to PC5) Port are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PC0 to PC5 input ports. It also sets all bits ...
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Port C1, C4 (RXD0, 1) Port C1 and C4 are I/O port pins and can also be used as RXD input for the serial channels. In case of use RXD0/RXD1 possible to logical invert by setting the ...
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PC Bit symbol (0023H) Read/Write After reset 7 6 PCCR Bit symbol (0026H) Read/Write After reset Function 7 6 Bit symbol PCFC (0027H) Read/Write After reset Function 7 6 Bit symbol PCODE (0028H) Read/Write After reset Function Note ...
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Port D (PD0 to PD7) Port 8-bit output port. Resetting sets the output latch and PD0 to PD7 pin output 1. In addition to functioning as output port, port D also function as ...
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PD Bit symbol PD7 PD6 (0029H) Read/Write R/W After reset PDFC Bit symbol PD7F PD6F (002AH) Read/Write W After reset 0 0: Port Function 0: Port 1: ALARM at <PD6> MLDALM ...
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Port E (PE0 to PE7) Port 8-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PECR. Resetting, the control register PECR to 0 and sets Port E ...
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Port F (PF0 to PF7) Port 8-bit output port. Resetting sets the output latch and PF0 to PF7 pin output 1. In addition to functioning as output port, port F also function as ...
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Chip Select/Wait Controller On the TMP91C820A, four user-specifiable address areas ( bus width and the number of waits can be set independently for each address area ( and others). The pins to (which can also function as port pins ...
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Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper eight bits (A23 to A16) of ...
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Memory address mask registers Figure 3.6.3 shows the memory address mask registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of ...
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Setting memory start addresses and address areas Figure 3.6.4 shows an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set 01H in memory start address register MSAR0<S23:16> (Corresponding to the upper 8 bits ...
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Address area size specification Table 3.6.1 shows the relationship between CS area and area size. “∆” indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a ...
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Chip Select/Wait Control Registers 7 6 B0CS Bit symbol B0E (00C0H) Read/Write W After reset 0 Read- 0: Disable modify- Function 1: Enable write instructions are prohibited. B1CS Bit symbol B1E (00C1H) Read/Write W After reset 0 Read- 0: Disable ...
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Master enable bits Bit 7 (<B0E>, <B1E>, <B2E> or <B3E> chip select/wait control register is the master bit, which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables ...
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Table 3.6.2 Dynamic Bus Sizing xxxx: Indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for these bits goes to high impedance; also, that the write strobe signal for ...
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Wait control Bits (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, <BEXW0:2> chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait ...
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If a CS0 to S3 address is specified which is actually an internal I/O and RAM area address, the CPU accesses the internal address area and no chip select signal is output on any of the Example: In this example ...
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TMP91C820A RD SRLB SRUB SRWR CS0 D [15:0] A0 Not connect Figure 3.6.7 How to Connect to 16-Bit SRAM for TMP91C820A 91C820A-107 TMP91C820A 16-bit SRAM OE LDS UDS R/W CE I/O [16: 2008-02-20 ...
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Timers (TMRA) The TMP91C820A features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. • 8-bit ...
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Block Diagrams Figure 3.7.1 TMRA01 Block Diagram 91C820A-109 TMP91C820A 2008-02-20 ...
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Figure 3.7.2 TMRA23 Block Diagram 91C820A-110 TMP91C820A 2008-02-20 ...
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Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided by 4 and input to this prescaler. φT0 can be either f fc/16 and is selected using the prescaler ...
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Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator ...
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Comparator (CP0) The comparator compares the value counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If ...
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SFRs 7 6 TA01RUN Bit symbol TA0RDE (0100H) Read/Write R/W After reset 0 Function Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA01RUN are ...
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TA01MOD Bit symbol TA01M1 TA01M0 (0104H) Read/Write After reset 0 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA01 Mode Register PWM01 PWM00 ...
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TA23MOD Bit symbol TA23M1 TA23M0 (010CH) Read/Write After reset 0 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA23 Mode Register PWM21 PWM20 ...
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TA1FFCR Bit symbol (0105H) Read/Write After reset Function Read- modify- write instructions are prohibited. TMRA1 Flip-Flop Control Register TA1FFC1 TA1FFC0 R/W 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care Inverse ...
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TA3FFCR Bit symbol (010DH) Read/Write After reset Function Read- modify- write instructions are prohibited. TMRA3 Flip-Flop Control Register TA3FFC1 TA3FFC0 R/W 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care Inverse ...
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TA0REG bit Symbol (0102H) Read/Write After reset TA1REG bit Symbol (0103H) Read/Write After reset TA2REG bit Symbol (010AH) Read/Write After reset TA3REG bit Symbol (010BH) Read/Write After reset Note: The above registers are prohibited read-modify-write instruction. TMRA register ...
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Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. a. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first ...
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Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.2 µ s square wave ...
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Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up counter 1 2 ...
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Pairing the two 8-bit timers TMRA0 and TMRA1 configures a 16-bit interval timer. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD<TA01M1:0> to 01. In 16-bit timer mode, the ...
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PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active-low or active-high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses ...
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In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be ...
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Example: To generate 1/4 duty 50 kHz pulses ( MHz): 20 µs * Clock state Calculate the value, which should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t ...
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PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output ...
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In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match ...
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Select Select Gear value system prescaler <GEAR2:0> clock clock <SYSCK> <PRCK1:0> 1 (fs) XXX 15.6 ms 62.5 ms 250 ms 31.3 ms 125 ms 500 ms 62.5 ms 250 ms 14.2 µs 56.8 µs 000 (fc) 28.4 µs 001 (fc/2) ...
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LCDC and MELODY/ALARM circuit supply mode This function can operate only TMRA3. It can use LCDC or MELODY/ALARM source clock TA3 clock generated by TMRA3. And keep the rule under below. OPERATE 1. Clock generate by timer 3 2. ...
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External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 136 Mbytes by having 4 local areas. Address pins to external memory are 2 extended address bus pins (EA24, EA25) and 8 extended chip ...
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Recommendable Memory Map The recommendation logic address memory map at the time of variety extension memory correspondence is shown in Figure 3.8.1. And, a physical-address map is shown in Figure 3.8.2. However, when memory area is less than 16 ...
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LOCAL0 LOCAL1 CS3 CS1 for data RAM for option (SDRAM program ROM non support) (SDRAM support) (8 Mbytes) (16 Mbytes) BANK0 BANK0 BANK1 BANK2 BANK1 BANK3 BANK4 BANK2 BANK5 BANK6 BANK3 BANK7 800000H BANK4 BANK5 BANK6 BANK7 1000000H Reset and ...
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Explanation of SFR There are 4 registers; LOCAL0 to LOCAL3. Each register is for enabling bank and setting bank. Setup LOCAL registers in common area. And, a combination pin and the CS/WAIT controller need to be set. When CPU ...
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CS0 CS1 Data Address TMP91C820A , ( , : SRAM HWR SDCLK, SDCKE, SDLDQM, SDUDQM , , SDCS SDRAS SDCAS SDWE CS2 EA24, EA25 CS3 * In case of 16-bit bus memory TMP91C820A Memory Control signals Control signals ...
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Setting ;CS0 LD (MSAR0),00H LD (MAMR0),FFH LD (B0CS),89H ;CS1 LD (MSAR1),40H LD (MAMR1),FFH LD (B1CS),83H ;CS2 LD (MSAR2),C0H LD (MAMR2),7FH LD (B2CS),C3H ;CS3 LD (MSAR3),80H LD (MAMR3),7FH LD (B3CS),85H ;CSX LD (BEXCS),00H ;Port LD (P6FC),3FH LD (P6FC2),02H to LDW ...
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Operation ; ***** CS2 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H ORG 800000H ORG A00000H ORG C00000H ORG E00000H LD (LOCAL3),85H LDW HL,(800000H) LD (LOCAL3),88H LDW BC,(800000H) to ORG FFFFFFH CS3 ; ***** ***** ORG 0000000H ORG ...
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Operation ;***** CS2 ***** ORG 000000H ; Program ROM: Start address at BANK0 of LOCAL2 ORG 200000H ; Program ROM: Start address at BANK1 of LOCAL2 NOP ; Operation at BANK1of LOCAL2 to ; Jump to BANK7( = COMMON2) ...
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At Figure 3.8.7, it shows example of program jump. In the same way with before example, two dot line squares show each and ’s (SDCS) SDRAM. Program start from E00000H COMMON address, firstly, write to CS1 BANK register of LOCAL2 ...
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Serial Channels TMP91C820A includes three serial I/O channels. For each channels either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. (Channel 2 can be selected only UART mode.) • I/O interface mode • UART ...
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Mode 0 (I/O interface mode) Bit0 Transfer direction • Mode 1 (7-bit UART mode) Start Bit0 No parity 1 2 Parity Start Bit0 1 2 • Mode 2 (8-bit UART mode) No parity Start Bit0 1 ...
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Block Diagrams Figure 3.9 block diagram representing serial channel 0. Prescaler φ φT2 φT8 φT32 Serial clock generation circuit BR0CR <BR0CK1, 0> BR0CR BR0ADD <BR0S3:0> <BR0K3:0> φT0 φT2 φT8 φT32 BR0CR ...
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Prescaler φ φ T2 φ T8 φ T32 Serial clock generation circuit BR1CR <BR1CK1:0> BR1CR BR1ADD <BR1S3:0> <BR1K3:0> φ T0 φ T2 φ T8 φ T32 BR1CR <BR1ADDE> Baud rate generator f SYS ...
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Prescaler φ φ T2 φ T8 φ T32 Serial clock generation circuit BR2CR <BR2CK1:0> BR2CR BR2ADD <BR2S3:0> <BR2K3:0> φ T0 φ T2 φ T8 φ T32 BR2CR <BR2ADDE> Baud rate generator f SYS ...
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Operation of Each Circuit (1) Prescaler, prescaler clock selects There is a 6-bit prescaler for waking serial clock. The clock selected using SYSCR<PRCK1:0> is divided by 4 and input to the prescaler as φT0. The prescaler can be run ...
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Baud rate generator The baud rate generator is a circuit, which generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is ...
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Integer divider (N divider) For example, when the source clock frequency (fc) = 12.288 MHz, the input clock frequency = φT2 (fc/16), the frequency divider N (BR0CR<BR0S3:0> and BR0CR<BR0ADDE> the baud rate in UART mode ...
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Table 3.9.3 Transfer Rate Selection (When baud rate generator is used and BR0CR<BR0ADDE> [MHz] Frequency Divider N (BR0CR<BR0S3:0>) 9.830400 2 ↑ 4 ↑ 8 ↑ 0 12.288000 5 ↑ A 14.745600 2 ↑ 3 ↑ 6 ↑ ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> the basic clock is generated by dividing the output ...
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The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 bits or 8 ...
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Handshake function Use of pin allows data can be sent in units of one frame; thus, overrun CTS errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD<CTSE> setting. When the CTS0 transmission is halted until ...
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Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty and generates ...
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Timing generation a. In UART mode Receiving Mode 9 Bits (Note) Interrupt timing Center of last bit (Bit8) Framing error timing Center of stop bit Parity error timing − Overrun error timing Center of last bit (Bit8) Note: In ...
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SFRs 7 Bit symbol TB8 CTSE SC0MOD0 Read/Write (0202H) After reset 0 Function Transfer Handshake data bit8 0: CTS disable 1: CTS enable Figure 3.9.8 Serial Mode Control Register (Channel 0, SC0MOD0 RXE WU SM1 ...
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Bit symbol TB8 CTSE SC1MOD0 Read/Write (020AH) After reset 0 Function Transfer Handshake data bit8 0: CTS disable 1: CTS enable Figure 3.9.9 Serial Mode Control Register (Channel 1, SC1MOD0 RXE WU SM1 R/W 0 ...
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Bit symbol TB8 SC2MOD0 Read/Write (0212H) After reset 0 Function Transfer Always data bit8 write “0”. Figure 3.9.10 Serial Mode Control Register (Channel 2, SC2MOD0 − RXE WU SM1 R Receive ...
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Bit symbol RB8 EVEN SC0CR Read/Write R (0201H) After reset Undefined 0 Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading, do not test only a single bit with ...
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Bit symbol RB8 EVEN SC1CR Read/Write R (0209H) After reset Undefined 0 Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading, do not test only a single bit with ...
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Bit symbol RB8 EVEN SC2CR Read/Write R (0211H) After reset Undefined 0 Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading, do not test only a single bit with ...
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Bit symbol BR0ADDE BR0CR Read/Write (0203H) After reset 0 0 Function Always + (16 − K)/16 write “0”. division 0: Disable 1: Enable + (16 − K)/16 division enable 0 Disable 1 Enable 7 6 BR0ADD Bit ...
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Bit symbol BR1ADDE BR1CR Read/Write (020BH) After reset 0 0 Function Always + (16 − K)/16 write “0”. division 0: Disable 1: Enable + (16 − K)/16 division enable 0 Disabled 1 Enabled 7 6 Bit symbol ...
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Bit symbol BR2ADDE BR2CR Read/Write (0213H) After reset 0 0 Function Always + (16 − K)/16 write “0”. division 0: Disable 1: Enable + (16 − K)/16 division enable 0 Disabled 1 Enabled 7 6 Bit symbol ...
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TB7 TB6 TB5 SC0BUF (0200H RB7 RB6 RB5 Note: Prohibit read-modify-write for SC0BUF. Figure 3.9.17 Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF) 7 Bit symbol I2S0 FDPX0 SC0MOD1 Read/Write R/W R/W (0205H) After reset ...
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TB7 TB6 TB5 SC2BUF (0210H RB7 RB6 RB5 Note: Prohibit read-modify-write for SC2BUF. Figure 3.9.21 Serial Transmission/Receiving Buffer Registers (Channel 2, SC2BUF) 7 Bit symbol I2S2 FDPX2 SC2MOD1 Read/Write R/W R/W (0215H) After reset ...
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Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK ...
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Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all data is output, INTES0<ITX0C> will be ...
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Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to receiving buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit ...
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Transmission and receiving (Full duplex mode) When the full duplex mode is used, set the level of receive interrupt to 0 and set enable the level of transmit interrupt. In the transmit interrupt program, read the receiving buffer before ...
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Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting the serial channel mode register SC0MOD0<SM1:0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled ...
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Clock state Main settings ← − − − − − − 0 − PCCR ← − SC0MOD ← ...
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Protocol a. Select 9-bit UART mode on the master and slave controllers. b. Set the SC0MOD0<WU> bit on each slave controller enable data receiving. c. The master controller transmits one-frame data including the 8-bit select code for ...
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Example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. SYS TXD RXD TXD Master Slave 1 Select code 00000001 Since Serial Channels 0 and 1 operate in exactly the ...
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Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.30 shows the block diagram. Transmisison data IR modulator SIO0 Modem Receive data IR demodulator TMP91C820A Figure 3.9.30 Block Diagram (1) Modulation of the ...
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SFR Figure 3.9.33 shows the control register SIRCR. Set the data SIRCR during SIO0 is stopping. The following example describes how to set this register: 1) SIO setting ↓ (SIRCR), 07H 3) LD (SIRCR), 37H ↓ 4) ...
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Bit symbol PLSEL RXSEL SIRCR (0207H) Read/Write After reset 0 0 Select Receive Function transmit data pulse width 0: H pulse 0: 3/ pulse 1: 1/16 Figure 3.9.33 IrDA Control Register TXEN ...
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Serial Bus Interface (SBI) The TMP91C820A has a one-channel serial bus interface which employs a clocked synchronous 8-bit SIO mode and an I The serial bus interface is connected to an external device through P71 (SDA) and P72 (SCL) ...
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Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status. • Serial bus interface control register 1 (SBI0CR1) • Serial bus interface control register 2 (SBI0CR2) • Serial ...
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I C Bus Mode Control The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the Bit symbol BC2 BC1 SBI0CR1 (0240H) Read/Write W After ...
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Bit symbol MST TRX SBI0CR2 (0243H) Read/Write After reset 0 0 Master/ Transmitter/ Function Prohibit slave receiver read- selection selection modify- write Note 1: Reading this register function as SBI0SR register. Note 2: Switch a mode to port ...
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Bit symbol MST TRX SBI0SR (0243H) Read/Write After reset 0 0 Master/ Transmitter/ Function slave receiver status status Prohibit monitor monitor read- modify- write Note: Writing in this register functions as SBI0CR2. Figure 3.10.5 Registers for the I ...
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SBI0BR0 Bit symbol I2SBI0 (0244H) Read/Write W R/W After reset 0 0 Prohibit Always read- IDLE2 Function modify- write “0”. 0: Stop write 1: Run 7 6 − SBI0BR1 Bit symbol P4EN (0245H) Read/Write W W After ...
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Control Bus Mode (1) Acknowledge mode specification Set the SBI0CR1<ACK> for operation in the acknowledge mode. The TMP91C820A generates an additional clock pulse for an acknowledge signal when operating in master mode. In ...
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Clock synchronization In the I C bus mode, in order to wired-AND a bus, a master device which pulls 2 down a clock line to low level, in the first place, invalidate a clock pulse of another master device ...
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Transmitter/receiver selection Set the SBI0CR2<TRX> for operating the TMP91C820A as a transmitter. Clear the <TRX> for operation as a receiver. When data with an addressing format is transferred in slave mode, when a slave address ...
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Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTSBI) occurs, the SBI0CR2 <PIN> is cleared to 0. During the time that the SBI0CR2<PIN> the SCL line is pulled down to the low ...
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The TMP91C820A compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBI0SR<AL> is set to 1. ...
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Software reset function The software reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. An internal reset signal pulse can be generated by setting SBI0CR2<SWRST1:0> and 01. This initializes ...
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Data Transfer Bus Mode (1) Device initialization Set the SBI0BR1<P4EN>, SBI0CR1<ACK, SCK2:0>, set SBI0BR1 to 1 and clear bits and 3 in the SBI0CR1 to 0. Set a slave address <SA6:0> and ...
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Check the <MST> by the INTSBI interrupt process after the 1-word data transfer is completed, and determine whether the mode is a master or slave. If <MST> (Master mode) a. Check the <TRX> and ...
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When the <TRX> (Receiver mode) When the next transmitted data is other than 8 bits, set <BC2:0> again. Set <ACK> and read the received data from SBI0DBR to release the SCL line (Data which is read ...
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If <MST> (Slave mode the slave mode the TMP91C820A operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBI interrupt request occurs when the TMP91C820A receives a ...
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Stop condition generation When the SBI0SR<BB> is “1”, the sequence of generating a stop condition is started by setting “111” to the SBI0CR2<MST, TRX, PIN> and “0” to the SBI0CR2<BB>. Do not modify the contents of the SBI0CR2<MST, TRX, ...
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Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data. The following explains how to restart when the TMP91C820A is in the master mode. Clear 0 to ...
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Clocked Synchronous 8-Bit SIO Mode control The following registers are used to control and monitor the operation status when the serial bus interface (SBI) is being operated in clocked synchronous 8-bit SIO mode Bit symbol SIOS SIOINH ...
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Bit symbol SBI0CR2 (0242H) Read/Write After reset Prohibit Function read- modify- write Note 1: Set the SBI0CR1<BC2:0> 000 before switching to a clocked synchronous 8-bit SIO mode. Note 2: Please always write “00“ to SBICR2<1:0> Bit ...
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Bit symbol I2SBI0 SBI0BR0 (0244H) Read/Write W R/W After reset 0 0 Prohibit Always IDLE2 Function read- write “0”. 0: STOP modify- write 1: RUN 7 6 − Bit symbol P4EN SBI0BR1 (0245H) Read/Write W W After ...
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Serial Clock a. Clock source SBI0CR1<SCK2:0> is used to select the following functions: Internal clock In internal clock mode one of seven frequencies can be selected. The serial clock signal is output to the outside on the SCK pin. ...
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Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. Leading edge shift Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK ...