TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 359

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(2) Points of note
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
k.
AM0 and AM1 pins
active.
EMU0 and EMU1
Reserved address areas
Warm-up counter
an external oscillator. As a result a time equivalent to the warm-up time elapses between
input of the release request and output of the system clock.
Programmable pull-up resistance
are set for use as input ports. When the ports are set for use as output ports, they cannot be
turned ON/OFF by a program.
Consequently read-modify-write instructions are prohibited.
Watchdog timer
watchdog timer is not to be used, disable it.
AD converter
reduce power consumption. When STOP mode is used, disable the resistor using the
program before the HALT instruction is executed.
CPU (Micro DMA)
registers in the CPU (e.g., the transfer source address register (DMASn)).
Undefined SFR
POP SR instruction
Releasing the HALT mode by requesting an interruption
INT3, INTKEY, INTRTC, INTALM0 to INTALM4) which can release the HALT mode may
not be able to do so if they are input during the period CPU is shifting to the HALT mode
(for about 5 clocks of f
(In this case, an interrupt request is kept on hold internally.)
status can be released without difficulty. The priority of this interrupt is compared with
that of the interrupt kept on hold internally, and the interrupt with higher priority is
handled first followed by the other interrupt.
This pin is connected to the V
Open pins.
The TMP91C820A does not have any reserved areas.
The warm-up counter operates when STOP mode is released, even if the system is using
The programmable pull-up resistor can be turned ON/OFF by a program when the ports
The data registers (e.g., P5) are used to turn the pull-up/pull-down resistors ON/OFF.
The watchdog timer starts operation immediately after a reset is released. When the
The string resistor between the VREFH and VREFL pins can be cut by a program so as to
Only the “LDC cr, r” and “LDC r, cr” instructions can be used to access the control
The value of an undefined bit in an SFR is undefined when read.
Please execute the POP SR instruction during DI condition.
Usually, interrupts can release all halt status. However, the interrupts (
If another interrupt is generated after it has shifted to the HALT mode completely, halt
FPH
) with IDLE1 or STOP mode (IDLE2 is not applicable to this case).
91C820A-357
CC
or the V
SS
pin. Do not alter the level when the pin is
TMP91C820A
NMI
2008-02-20
, INT0 to