TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 168

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Timing to write
transmission data
SCLK1 output
(<SCLKS>=0
Rising edge mode)
ITX1C
(INTTX1
Interrupt request)
SCLK1 output
(<SCLKS>=1
Falling edge mode)
TXD1
(INTTX1
Interrupt request)
TXD1
SCLK1input
(<SCLKS> = 0
Rising edge mode)
SCLK1 input
(<SCLKS> = 1
Falling edge mode)
ITX1C
Figure 3.9.25 Transmitting Operation in I/O Interface Mode (SCLK0 output mode)
Figure 3.9.26 Transmitting Operation in I/O Interface Mode (SCLK0 input mode)
a.
Transmission
TXD0 and SCLK0 pins respectively each time the CPU writes the data to the
transmission buffer. When all data is output, INTES0<ITX0C> will be set to
generate the INTTX0 interrupt.
input becomes active after the data has been written to the transmission buffer by
the CPU.
interrupt.
In SCLK output mode 8-bit data and a synchronous clock are output on the
In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0
When all data is output, INTES0<ITX0C> will be set to generate INTTX0
Bit0
Bit0
91C820A-166
(Channel 0)
(Channel 0)
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP91C820A
2008-02-20
(Internal clock
timing)