TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 2

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

**CAUTION**
INT0 to INT3, INTRTC, INTALM0 to INTALM4, INTKEY), which can release the
HALT mode may not be able to do so if they are input during the period CPU is
shifting to the HALT mode (for about 5 clocks of f
(IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on
hold internally.)
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
How to release the HALT mode
Thank you very much for making use of Toshiba microcomputer LSIs.
Especially, take care below cautions.
Usually, interrupts can release all halts status. However, the interrupts = (
If another interrupt is generated after it has shifted to HALT mode completely,
Preface
FPH
) with IDLE1 or STOP mode
NMI
,