TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 255

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(3) Timer out LCDCK
(TA3OUT) outputs from internal TMRA23.
under a decimal point.
timer out LCDCK.)
(e.g.)
LCD source clock (LCDCK) can select low frequency (fs: 32.768 [kHz]) or timer out
The next equation calculates frame period.
Source clock for LCDC defines as XT [Hz] and then this t
Therefore if you set the frame period at 70 [Hz] under 128 COM,
XT should be above value.
In order to make XT = 26880 [Hz] under fc = 6 [MHz] with φT1 of timer 3,
in short, XT = fc/(T3 × 2 × 8) [Hz]
However T3 = (TA3REG) is 13.95 after calculate, it’s impossible to set the value
So if T3 = (TA3REG) is set 0DH, XT = 28846 [Hz]. And because of D = 3,
Further if f
(You have to use frame frequency setting, frame invert adjustment function and
Monochrome: Frame period = 70 [Hz]
4 or 8 or 16 gray: Frame period = 140 [Hz]
Reference: To maintain quality for display, please refer to following value for each
Here indicates the method that frame period is set 70 [Hz] by selecting
TA3OUT for source clock of LCD. (fc = 6 [MHz], 128 COM)
Frame period = 1/(t
t
XT = 128 × 3.5 × 70
LP
Frame period = 28846/(128 × 3)
Frame period = 28846/(136 × 3)
1/XT = T3 × 2 × 8/fc [s]
= 26880 [Hz]
= D/XT
FP
gray scale.
is 136 (COM + 8) with correction,
= 70.70 [Hz]
= 75.12 [Hz]
91C820A-253
LP
× f
FP
) [Hz]
T3: The value of timer register (TA3REG)
t
D: The value is 3 at 128 COM
LP
: The period of D2BLP
LP
represents
TMP91C820A
2008-02-20