TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 127

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

TA0REG-WR
(Value to be compared)
Match with TA0REG
Match with TA1REG
TA01RUN<TA0RDE>
and up counter
Register buffer
TA01MOD<TA0CLK1:0>
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
TA01RUN<TA1RUN> should be set to 1 so that UC1 is set for counting.
will be shifted into TA0REG each time TA1REG matches UC0.
varied).
TA0IN
φ T1
φ T4
φ T16
TA0REG
In this mode a programmable square wave is generated by inverting the timer
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode,
Figure 3.7.14 shows a block diagram representing this mode.
If the TA0REG double buffer is enabled in this mode, the value of the register buffer
Use of the double buffer facilitates the handling of low-duty waves (when duty is
Selector
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
Selector
Shift trigger
Figure 3.7.15 Operation of Register Buffer
Register buffer
(Up counter = Q
Comparator
TA0REG
Q
up counter (UC 0)
Internal data bus
1
91C820A-125
8-bit
1
)
Q
2
Comparator
TA1REG
TA01RUN<TA0RUN>
(Up countner = Q
Shift from register buffer
2
)
Q
TA1OUT
2
TA0REG (Register buffer)
write
TA1FF
Q
3
Inversion
TA1FFCR<TA1FFIE>
INTTA0
INTTA1
TMP91C820A
2008-02-20