TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 341

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

SC0MOD0
SC0MOD1
Symbol
Symbol
SC0BUF
BR0ADD
(8-1) UART/SIO channel 0
(8-2) IrDA
SC0CR
BR0CR
SIRCR
(8) UART/serial channel (1/3)
IrDA
control
register
Serial
channel 0
buffer
Serial
channel 0
control
Serial
channel 0
mode0
Baud rate
control
Serial
channel 0
K setting
register
Serial
channel 0
mode1
Name
Name
Address
Address
(Prohibit
RMW)
200H
201H
202H
203H
204H
205H
207H
Transmission
data bit8
Transmission
pulse width
IDLE2
0: Stop
1: Operate
0: 3/16
1: 1/16
Undefined
Receiving
data bit8
Always
write “0”.
RB7/TB7
PLSEL
I2S0
RB8
TB8
R/W
R/W
7
R
0
−
0
0
7
0
1: (16 − K)/16
Duplex
0: Half
1: Full
Parity
0: Odd
1: Even
1: CTS
BR0ADDE BR0CK1
Receiving
data
0: H pulse
1: L pulse
RB6/TB6
FDPX0
divided
enable
EVEN
RXSEL
CTSE
enable
R/W
R/W
6
0
0
0
0
6
0
91C820A-339
R/W
Transmission
1: Parity
1: Receive
00: φT0
01: φT2
10: φT8
11: φT32
0: Disable
1: Enable
RB5/TB5
enable
TXEN
enable
RXE
R/W
PE
5
0
0
5
0
R (Receiving)/W (Transmission)
0
Receiving
0: Disable
1: Enable
1: Wakeup
RB4/TB4
BR0CK0
Overrun
RXEN
OERR
enable
R/W
WU
R (Cleared to 0 by reading)
4
0
4
0
0
Undefined
R/W
R/W
Set the effective SIRRxD pulse width
Pulse width more than 2x × (Set value + 1) + 100
ns
Possible: 1 to 14
Not possible: 0, 15
00: I/O Interface
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
RB3/TB3
SIRWD3
1: Error
BR0S3
BR0K3
PERR
Parity
SM1
3
3
0
0
0
0
0
Setting of the divided frequency “N”
(Divided by N = (16 − K)/16)
Sets frequency divisor “K”
RB2/TB2
Framing
SIRWD2
BR0S2
BR0K2
FERR
SM0
2
0
0
0
0
2
0
(0 to F)
R/W
R/W
0:SCLK0↑
1:SCLK0↓
00: TA0TRG
01: Baud rate
10: Internal clock f
11: External clock
RB1/TB1
SIRWD1
SCLKS
BR0S1
BR0K1
SC1
generator
SCLK0
TMP91C820A
1
0
0
0
0
1
0
2008-02-20
R/W
1: Input
BR0S0
RB0/TB0
BR0K0
SIRWD0
SCLK0
pin
SC0
IOC
0
0
0
0
0
0
0
SYS