TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 151

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(4) Receiving counter
(5) Receiving control
(3) Serial clock generation circuit
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This circuit generates the basic clock for transmitting and receiving data.
In I/O interface mode
In UART mode
In I/O interface mode
In UART mode
generated by dividing the output of the baud rate generator by 2, as described
previously.
falling edge will be detected according to the setting of the SC0CR<SCLKS>
register to generate the basic clock.
clock, the internal system clock f
or the external clock (SCLK0) is used to generate the basic clock SIOCLK.
counts up the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1
bit of data; each data bit is sampled three times – on the 7th, 8th and 9th clock
cycles.
majority rule.
9th clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0
and 1 is taken to be 0.
sampled on the rising or falling edge of the shift clock which is output on the
SCLK0 pin, according to the SC0CR<SCLKS> setting.
sampled on the rising or falling edge of the SCLK0 input, according to the
SC0CR<SCLKS> setting.
majority rule. Received bits are sampled three times; when two or more out of
three samples are 0, the bit is recognized as the start bit and the receiving
operation commences.
majority rule.
In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is
In SCLK input mode with the setting SC0CR<IOC> = 1, the rising edge or
The SC0MOD0<SC1:0> setting determines whether the baud rate generator
The receiving counter is a 4-bit binary counter used in UART mode, which
The value of the data bit is determined from these three samples using the
For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and
In SCLK output mode with the setting SC0CR<IOC> = 0, the RXD0 signal is
In SCLK input mode with the setting SC0CR<IOC> = 1, the RXD0 signal is
The receiving control block has a circuit, which detects a start bit using the
The values of the data bits that are received are also determined using the
91C820A-149
SYS
, the match detect signal from timer TMRA0
TMP91C820A
2008-02-20