TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 164

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

BR2ADD
(0213H)
(0214H)
BR2CR
0
1
+ (16 − K)/16 division enable
BR2ADD
<BR2K3:0>
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Disabled
Enabled
1111 (K = 15)
Note1:Availability of +(16-K)/16 division function
Note2:Set BR2CR <BR2ADDE> to 1 after setting K (K = 1 to 15) to BR2ADD<BR2K3:0> when +(16-K)/16 division
0001 (K = 1)
Figure 3.9.16 Baud Rate Generator Control (Channel 2, BR2CR, BR2ADD)
0000
to
function is used. Writes to unused bits in the BR2ADD register do not affext operation, and undefined data is
read from these unused bits
BR2CR
<BR2S3:0>
Always
write “0”.
Baud rate generator frequency divisor setting
The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function. Don’t use in
I/O interface mode.
N
2 to 15
1 , 16
7
−
0
7
+ (16 − K)/16
division
0: Disable
1: Enable
BR2ADDE
0000 (N = 16)
0001 (N = 1)
6
0
6
Disable
Disable
UART mode
BR2CR<BR2ADDE> = 1
or
○
×
00: φT0
01: φT2
10: φT8
11: φT32
00
01
10
11
BR2CK1
Input clock selection for baud rate generator
5
0
5
N + (16 − K)/16
1111 (N = 15)
91C820A-162
0010 (N = 2)
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
Disabled by
Disable
to
BR2CK0
I/O mode
4
4
0
×
×
R/W
0001 (N = 1) (Only UART)
BR2CR<BR2ADDE> = 0
BR2K3
BR2S3
3
0
3
0
1111 (N = 15)
0000 (N = 16)
Setting of the divided frequency “N”
Divided by N
(Divided by N + (16 − K)/16)
Sets frequency divisor “K”
to
BR2S2
BR2K2
2
2
0
0
(0 to F)
R/W
BR2S1
BR2K1
1
1
0
0
BR2S0
BR2K0
TMP91C820A
0
0
0
0
2008-02-20