TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 47

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.4.2
Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.
Micro DMA Processing
DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the
highest priority level for maskable interrupts (Level 6), regardless of the priority level of
the particular interrupt source.
of CPU, when CPU is a state of standby by HALT instruction, the requirement of micro
DMA will be ignored (Pending).
(1) Micro DMA operation
In addition to general-purpose interrupt processing, the TMP91C820A supprots a micro
Because the micro DMA function has been implemented with the cooperative operation
In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking
“Interrupt specified by micro DMA start vector” (in the Figure 3.4.1) and reading interrupt vector with
setting below. The vector shifts to that of INTyyy at the time.
This is because the priority level of INTyyy is higher than that of INTxxx.
In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished.
And INTyyy is generated regardless of transfer counter of micro DMA.
INTxxx: level 1 without micro DMA
INTyyy: level 6 with micro DMA
DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at
interrupt priority level 6 and starts processing the request. The four micro DMA
channels allow micro DMA processing to be set for up to four types of interrupts at any
one time.
channel is cleared. The data are automatically transferred from the transfer source
address to the transfer destination address set in the control register, and the transfer
counter is decremented by 1. If the decremented counter reads other than 0, DMA
processing ends with no change in the value of the micro DMA start vector register. If
the decremented reading is 0, the micro DMA transfer end interrupt (INTTC0 to
INTTC3) passes from the CPU to the interrupt controller. In addition, the micro DMA
start vector register is cleared to 0, the next micro DMA is disabled and micro DMA
processing completes.
based on the interrupt priority level but on the channel number: the smaller the
channel number the higher the priority (Channel 0 (High) → Channel 3 (Low)).
between the clearing of the micro DMA start vector and the next setting,
general-purpose interrupt processing executes at the interrupt level set. Therefore, if
only using the interrupt for starting the micro DMA (Not using the interrupts as a
general-purpose interrupt), first set the interrupts level to 0 (Interrupt requests
disabled).
first set the level of the interrupt used to start micro DMA processing lower than all
the other interrupt levels. In this case, the cause of general interrupt is limited to the
edge interrupt. (Note)
interrupts is determined by the interrupt level and by the default priority.
When an interrupt request is generated by an interrupt source specified by the micro
When micro DMA is accepted, the interrupt request flip-flop assigned to that
If a micro DMA request is set for more than one channel at a time, the priority is not
If an interrupt request is triggered for the interrupt source in use during the interval
If using micro DMA and general-purpose interrupts together as described above,
As with other maskable interrupts, the priority of the micro DMA transfer end
91C820A-45
TMP91C820A
2008-02-20