TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 78

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

P6
(0012H)
P6FC
(0015H)
P6FC2
(001BH)
3.5.8
Note: Read-modify-write is prohibited for P6FC and P6FC2.
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Port 6 (P60 to P67)
latches of P60 to P61 and P63 to P67 are set to 1.
EA25), extend chip-select output (
output (
Port 60 to 67 are 8-bit output ports. Resetting sets output latch of P62 to 0 and output
Port 6 also function as chip-select output (
Writing 1 in the corresponding bit of P6FC, P6FC2 enables the respective functions.
Resetting reset the P6FC and P6FC2 to 0, and sets all bits to output ports.
Reset
SRUB
0: Port
1:
0: <P67F>
1:
(on bit basis)
P67F2
SRUB
CS2E
(on bit basis)
P67F
P6FC2 write
P6FC write
P67
Function
7
7
7
Function
control 2
1
P6 write
control
Output
lacth
,
SRLB
P6 read
0: Port
1:
0: <P66F>
1:
P66F2
SRLB
CS2D
P66F
), and SDRAM chip-select output (
P66
Figure 3.5.18 Register for Port 6
6
6
6
1
CS0
Port 6 Function Register 2
Figure 3.5.17 Port 6
0: Port
1: EA25
0: <P65F>
1:
SDCS
Port 6 Function Register
B
C
A
P65F2
,
CS2C
P65F
CS1
P65
91C820A-76
Selector
5
1
5
5
Port 6 Register
,
CS2A
,
CS2A
S
CS2
0: Port
1: EA24
0: <P64F>
1:
,
,
CS3
CS2B
P64F2
CS2B
P64F
,
P64
4
4
4
1
CS2B
, EA24, EA25,
,
CS2C
R/W
CS0
W
W
0
0
,
0: Port
1:
write “0”.
CS2C
Always
,
CS3
P63F
CS2D
P63
to
3
3
3
1
−
CS3
SRLB
,
,
CS2E
CS2D
SDCS
0: Port
1:
0: <P62F>
1:
), extend address output (EA24,
,
P62F2
SRUB
CS2
CS2A
P60 (
P61 (
P62 (
P63 (
P64 (EA24,
P65 (EA25,
P66 (
P67 (
P62F
P62
2
2
2
0
,
).
CS2E
CS0
CS1
CS2
CS3
SRUB
SRLB
0: Port
1:
1:
0: <P61F>
)
,
,
)
SDCS
CS2A
,
CS2C
,
), SRAM byte control
CS2B
CS1
P61F2
SDCS
CS2D
P61F
CS2E
P61
1
1
1
1
)
)
)
)
)
)
TMP91C820A
0: Port
1:
write “0”.
2008-02-20
Always
CS0
P60F
P60
0
0
1
0
−