TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 145

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TMP91xy20AFG

Manufacturer Part Number
TMP91xy20AFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy20AFG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M
Rom Combinations
8
Ram Combinations
8
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
77
Power Supply Voltage(v)
3.0 to 3.6
with PC5
with PC5
with PC4
Shared
Shared
Shared
SCLK1
SCLK1
RXD1
f
φ T0
SYS
I/O interface mode
SC1MOD0
<RXE>
φ T0
φ T2
φ T8
φ T32
RXDCLK
RB8
Serial clock generation circuit
Receive buffer 1 (Shift register)
<BR1CK1:0>
2
Receive buffer 2 (SC1BUF)
BR1CR
(Only UART ÷ 16)
φ T2
4
Prescaler
Receive
Receive
counter
<BR1S3:0>
control
8
BR1CR
φ T8 φ T32
16 32 64
Figure 3.9.3 Block Diagram of the Serial Channel 1
Baud rate
generator
<BR1ADDE>
BR1CR
BR1ADD
<BR1K3:0>
<OERR><PERR><FERR>
SC1MOD0
<WU>
Internal data bus
<PE>
Parity control
SC1CR
Error flag
÷ 2
SC1CR
91C820A-143
Serial channel
<EVEN>
(from TMRA0)
interrupt
TA0TRG
control
SC1MOD0
<SC1:0>
SC1CR
<IOC>
I/O
interface mode
UART
mode
SC1MOD0
TXDCLK
<SM1:0>
TB8
Transmission buffer (
(Only UART
Transmission
Transmision
counter
control
SIOCLK
÷
16)
SC1BUF)
SC1MOD0
<CTSE>
TMP91C820A
INT request
INTRX1
INTTX1
2008-02-20
Shared
with PC5
TXD1
Shared
with PC3
CTS1

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