TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 49

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
DMAR
Name
request
register
DMA
(2) Soft start function
(3) Transfer control registers
a micro DMA software start function that starts micro DMA on the generation of the
write cycle to the DMAR register.
bit, micro DMA doesn’t operate). At the end of transfer, the corresponding bit of the
DMAR register which support the end channel are automatically cleared to 0.
writing 1. If read “1”, micro DMA transfer isn’t started yet.
the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If
execute soft start during micro DMA transfer by interrupt source, micro DMA transfer
counter doesn’t change. Don’t use Read-modify-write instruction to avoid writing to
other bits by mistake.
following registers. An instruction of the form “LDC cr, r” can be used to set these
registers.
In addition to starting the micro DMA function by interrupts, TMP91C820A includes
Writing 1 to each bit of DMAR register causes micro DMA once (If write “0” to each
Only one channel can be set for DMA request at once. (Do not write 1 to plural bits)
When writing again 1 to the DMAR register, check whether the bit is 0 before
When a burst is specified by DMAB register, data is continuously transferred until
The transfer source address and the transfer destination address are set in the
Address
(Prohibit
RMW)
Channel 0
Channel 3
89H
DMAS0
DMAD0
DMAS3
DMAD3
32 bits
DMAC0
DMAC3
7
16 bits
DMAM0
DMAM3
8 bits
6
91C820A-47
DMA source address register 0.
DMA destination address register 0.
DMA counter register 0.
DMA mode register 0.
DMA source address register 3.
DMA destination address register 3.
DMA counter register 3.
DMA mode register 3.
5
4
DMAR3
3
0
DMAR2
2
0
DMA request
R/W
DMAR1
TMP91C820A
1
0
2008-02-20
DMAR0
0
0