TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 97

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

PE
(002CH)
PECR
(002DH)
PEFC
(002EH)
3.5.16
Note: Read-modify-write is prohibited for PECR and PEFC.
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Port E (PE0 to PE7)
output using the control register PECR. Resetting, the control register PECR to 0 and sets
Port E to input ports. It also sets all bits of the output latch register to 1.
data bus for LCD controller (LD0 to LD7). Above setting is used the function register
PEFC.
Port E is an 8-bit general-purpose I/O ports. Each bit can be set individually for input or
In addition to functioning as a general-purpose I/O port, port E can also function as an
PE7C
(on bit basis)
PE7F
(on bit basis)
Output latch
PE7
LD7 to LD0
Direction
PEFC write
7
7
7
PECR write
PE write
0
0
Function
control
Reset
control
PE read
S
PE6C
PE6F
PE6
Figure 3.5.44 Register for Port E
6
6
0
6
0
Data from external port (Output latch register is set to 1.)
A
B
Selector
Selector
Figure 3.5.43 Port E
Port E Function Register
Port E Control Register
0: Port 1: Data bus for LCDC (LD7 to LD0)
S
PE5C
PE5F
S
PE5
91C820A-95
Port E Register
5
5
5
0
0
A
B
0: Input 1: Output
PE4C
PE4F
PE4
4
4
4
0
0
R/W
W
W
PE3C
PE3F
PE3
3
3
0
3
0
PE2C
PE2F
PE2
2
2
2
0
0
PE0 to PE7
(LD0 to LD7)
PE1C
PE1F
PE1
1
1
1
0
0
TMP91C820A
2008-02-20
PE0C
PE0F
PE0
0
0
0
0
0