TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 181

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

SBI0CR2
Prohibit
read-
modify-
write
(0243H)
Note 1:
Note 2:
Bit symbol
Read/Write
After reset
Function
Reading this register function as SBI0SR register.
Switch a mode to port mode after confirming that the bus is free.
Switch a mode between I
via port are high level.
Master/
slave
selection
MST
7
0
Figure 3.10.4 Registers for the I
Transmitter/
receiver
selection
TRX
2
6
0
C bus mode and clock synchronous 8-bit SIO mode after confirming that input signals
Serial Bus Interface Control Register 2
W
Start/stop
condition
generation
BB
5
0
91C820A-179
Cancel
INTSBI
interrupt
request
PIN
4
1
Serial bus interface
operating mode selection
(Note 2)
Serial bus interface operating mode selection (Note 2)
INTSBI interrupt request
Start/stop condition generation
Transmitter/receiver selection
Master/slave selection
00 Port mode (Serial bus interface output disabled)
01 Clocked synchronous 8-bit SIO mode
10 I
11 (Reserved)
00: Port mode
01: SIO mode
10: I
11: (Reserved)
0
1
0
1
0
1
0
1
SBIM1
2
C Bus Mode
3
0
2
Don’t care
Cancel interrupt request
Generates the stop condition
Generates the start condition
Receiver
Transmitter
Slave
Master
C bus mode
2
W (Note 1)
C bus mode
SBIM0
2
0
Software reset generate
write 10 and 01, then an
internal reset signal is
generated.
SWRST1
1
0
W (Note 1)
SWRST0
TMP91C820A
0
0
2008-02-20