TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 203

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

b.
Figure 3.10.27 Transmitted Data Hold Time at End of Transmission
SCK pin
SIOF
SO pin
Note: When the transfer mode is changed, the contents of SBI0DBR will be lost. If the
8-bit receive mode
switching to receive mode. Data is received into the shift register via the SI pin
and synchronized with the serial clock, starting from the least significant bit
(LSB). When 8-bit data is received, the data is transferred from the shift register
to SBI0DBR. An INTSBI (Buffer full) interrupt request is generated to request
that the received data be read. The data is then read from SBI0DBR by the
interrupt service program.
function will be in effect until the received data has been read from SBI0DBR.
external clock pulse, the received data should be read from SBI0DBR before the
next serial clock pulse is input. If the received data is not read, any further data,
which is to be received, is canceled. The maximum transfer speed when an
external clock is used is determined by the delay time between the time when an
interrupt request is generated and the time when the received data is read.
service program or when <SIOINH> is set to 1. If <SIOS> is cleared to 0, received
data is transferred to SBI0DBR in complete blocks. The received mode ends when
the transfer is complete. In order to confirm whether data is being received
properly by the program, set SBI0SR<SIOF> to be sensed. <SIOF> is cleared to 0
when receiving has been completed. When it is confirmed that receiving has been
completed, the last data is read. When <SIOINH> is set to 1, data receiving stops.
<SIOF> is cleared to 0. (The received data becomes invalid, therefore no need to
read it.)
Set the control register to receive mode and set SBI0CR1<SIOS> to 1 for
When an internal clock is used, the serial clock will stop and the automatic wait
When an external clock is used, since shift operation is synchronized with an
Receiving of data ends when <SIOS> is cleared to 0 by the buffer full interrupt
mode must be changed, conclude data receiving by clearing <SIOS> to 0, read
the last data, and then change the mode.
Bit6
91C820A-201
Bit7
t
SODH
= Min 3.5/f
FPH
[s]
TMP91C820A
2008-02-20