TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 220

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.12.3
Operation
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be 0 cleared in software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (Runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-multifunction
program.
continues counting during bus release (when
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
Example: a. Clear the binary counter.
The watchdog timer generates an INTWD interrupt when the detection time set in the
The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter
When the device is in IDLE2 mode, the operation of WDT depends on the
b. Set the watchdog timer detection time to 2
c. Disable the watchdog timer.
WDCR
WDMOD ← 1 0 1 – – – – 0
WDMOD ← 0 – – – – – – 0
WDCR
← 0 1 0 0 1 1 1 0
← 1 0 1 1 0 0 0 1
91C820A-218
Write the clear code (4EH).
Clear WDTE to 0.
Write the disable code (B1H).
BUSAK
goes low).
17
/f
SYS
.
TMP91C820A
2008-02-20