TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 190

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

SCL line
SDA line
<PIN>
INTSBI interrupt
request
3.10.6
Data Transfer in I
(1) Device initialization
(2) Start condition and slave address generation
7 to 5 and 3 in the SBI0CR1 to 0.
to the I2C0AR.
BB> and set 1 to the <PIN>, 10 to the <SBIM1:0>.
Figure 3.10.13 Start Condition Generation and Slave Address Transfer
a.
b.
Start condtion
Set the SBI0BR1<P4EN>, SBI0CR1<ACK, SCK2:0>, set SBI0BR1 to 1 and clear bits
Set a slave address <SA6:0> and the <ALS> (<ALS> = 0 when an addressing format)
For specifying the default setting to a slave receiver mode, clear 0 to the <MST, TRX,
Master mode
follows.
and a direction bit to be transmitted to the SBI0DBR.
SBI0CR2<MST, TRX, BB, PIN>. Subsequently to the start condition, nine clocks
are output from the SCL pin. While eight clocks are output, the slave address and
the direction bit which are set to the SBI0DBR. At the 9th clock, the SDA line is
released and the acknowledge signal is received from the slave device.
<PIN> is cleared to 0. In the master mode, the SCL pin is pulled down to the
low-level while <PIN> is 0. When an interrupt request occurs, the <TRX> is
changed according to the direction bit only when an acknowledge signal is
returned from the slave device.
Slave mode
are output from the SCL pin, the slave address and the direction bit which are
output from the master device are received.
I2C0AR is received, the SDA line is pulled down to the low level at the 9th clock,
and the acknowledge signal is output.
<PIN> is cleared to 0. In slave mode the SCL line is pulled down to the low level
while the <PIN> = 0.
In the master mode, the start condition and the slave address are generated as
Check a bus free status (when <BB> = 0).
Set the SBI0CR1<ACK> to 1 (Acknowledge mode) and specify a slave address
When SBI0CR2<BB> = 0, the start condition are generated by writing 1111 to
An INTS2 interrupt request occurs at the falling edge of the 9th clock. The
In the slave mode, the start condition and the slave address are received.
After the start condition is received from the master device, while eight clocks
When a GENERAL CALL or the same address as the slave address set in
An INTSBI interrupt request occurs on the falling edge of the 9th clock. The
A6
1
2
C Bus Mode
A5
2
A4
3
Slave address + Direction bit
91C820A-188
A3
4
A2
5
A1
6
A0
7
R/
W
8
ACK
Output of master
Output of slave
TMP91C820A
9
Acknowledge
signal from a
slave device
2008-02-20